Cadence India eNewsletter
Cadence and Renesas Enhance Productivity with New System-Level Design Approach

Industry leaders join forces to move next-generation EDA technology from the lab to the real world
Trainings & Workshops
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Digital IC

Logic Equivalence Checking with Encounter Conformal EC-v7.1
17 Sep 2009 - 18 Sep 2009,
Bangalore, India

Detail Routing with NanoRoute Router - v7.1
29 Sep 2009 - 30 Sep 2009,
Bangalore, India

Custom IC

Virtuoso Platform Update Training: Infrastructure ; Analog & Physical Design - vIC6.1.3
14 Sep 2009 - 16 Sep 2009,
Bangalore, India


Basic SystemVerilog for Design and Verification - V8.1
14 Sep 2009 - 15 Sep 2009
Bangalore, India

AIncisive Comprehensive Coverage-v8.1
18 Sep 2009 - 18 Sep 2009,
Bangalore, India

IAssertion-based Verification using SVA in the Incisive Formal Verifier
24 Sep 2009 - 24 Sep 2009,
Bangalore, India

Silicon Package Board

Allegro Package Designer-v16.01
14 Sep 2009 - 15 Sep 2009,
Bangalore, India

September 2009 
  Encounter Digital IC Platform News
Tilera Adopts Broad Range of Cadence Solutions for Multicore Processor Design
Maker of Highly Scalable Multicore Embedded Processors Cites Comprehensive Technology and Service Support as Motives for Selecting Cadence More»
Cadence Low-Power Solution Selected for Global Unichip's PowerMagic Low-Power Design Methodology
PowerMagic 65-Nanometer Design Methodology Leverages Cadence End-to-End CPF-Based Low-Power Solution More»
  Virtuoso Custom IC Platform News
Things You Didn't Know About Virtuoso: RTFM
By Stacy Whiteman on August 25, 2009
Wait, don’t run away! In this case I really mean ’Read The Fantastic Man’. More»
UltraSim New SFE Application Note
The new Simulation Front End has been successfully implemented in Spectre and it is the Spectre default parser since MMSIM60. More»
  Incisive Verification Platform News
UMC Adopts Cadence 40-Nanometer Reference Flow for Low Power, Verification, Implementation and DFM-Aware Design
Cadence CPF-based Low Power Flow and Integrated DFM Capabilities Enable Simplified Advanced Node Design Methodology for UMC Customers More»
Incisive Enterprise Simulator: Low-Power Verification at Warp Speed
By Team genIES on September 09, 2009
Since your circuit always runs at low-power, your verification should too. More»
  Allegro SPB Platform News
What's Good About Split Parts in AMS Simulator? More Features in SPB16.2!
By Gerald “Jerry” Grzenia on Sep 3, 2009
This new SPB16.2 feature allows Allegro AMS Simulator (PSpice) customers to simulate split parts as single components. More»
What's Good About DEHDL Usability Improvements? The Secret's in the SPB16.2 Release!
By Gerald “Jerry” Grzenia on Aug 12, 2009
The Design Entry HDL (DEHDL) usability improvements are many and significant in the SPB16.2 release! More»