Cadence India eNewsletter

Novafora Reduces Startup Risks with the Cadence System Verification Solution
Trainings & Workshops
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Digital IC

Floorplanning, Physical Synthesis, Place and Route - V8.1
10 Aug 2009 - 12 Aug 2009,
Bangalore, India

Low Power Verification with Conformal-V5.0
13 Aug 2009,
Bangalore, India

Logic Equivalence Checking with Encounter Conformal EC-v7.1
27 Aug 2009 - 28 Aug 2009,
Bangalore, India

Custom IC

Virtuoso Platform Update Training: Infrastructure; Analog & Physical Design - vIC6.1.3
10 Aug 2009 - 12 Aug 2009,
Bangalore, India

Virtuoso XL Layout Editor-v5.1.41
18 Aug 2009 - 20 Aug 2009,
Bangalore, India


Specman Elite Basics for Verification Environment Users-v8.1
17 Aug 2009 - 18 Aug 2009
Bangalore, India

Assertion-based Verification using PSL in the Incisive Formal Verifier
25 Aug 2009 - 25 Aug 2009,
Bangalore, India

Incisive Unified Simulator
27 Aug 2009 - 28 Aug 2009,
Bangalore, India

Silicon Package Board

SystemC Fundamentals - v6.2
10 Aug 2009 - 12 Aug 2009,
Bangalore, India

August 2009 
  Encounter Digital IC Platform News
Hitachi Implements 50–Million Gate Design Using Cadence Encounter Digital Implementation System
Complex, Large–Scale Design is Fully Implemented in Five Weeks. More»
Cadence Delivers 28-Nanometer Design Capabilities to TSMC Reference Flow 10.0
Cadence Innovations in Low Power, Statistical and DFM Analysis,  More»
Cadence Achieves First-Silicon Results on 32nm Common Platform™ Technology
Improved Modeling Enables Encounter® Digital Implementation System to Accelerate Advanced Node Design More»
  Virtuoso Custom IC Platform News
Cadence Announces National Semiconductor Adoption of Virtuoso Simulation Solution for Complex Analog Designs
Virtuoso Accelerated Parallel Simulator Enables Accurate Simulation of Designs in Days or Hours More»
Litho Aware Device and Interconnect Extraction
Brajesh Heda, Lead App. Engineer, Cadence Design Systems, India.
Designers have started facing heat due to manufacturing variations in sub 90nm process technologies, which are not in their control. More»
UltraSim’s New Fast Digital Simulation Mode Application Note
In the past, UltraSim has offered 5 simulation modes, they differ in partitioning, solver integration method and device models More»
  Incisive Verification Platform News
Cadence Introduces First TLM–Driven Design and Verification Solution to Increase Engineering Productivity over RTL-based Flows
Solution Combines RTL/TLM Design with High–Level Synthesis, Mixed TLM/RTL Functional Verification and Equivalency Checking, Methodology, and Adoption Services. More»
OVM World Collaborates on Accellera’s Industry Solution for VIP Interoperability
Contributions from Cadence and Mentor Central to Accellera “Best Practices” Verification Guide More»
  Allegro SPB Platform News
What's Good About Allegro's Placement Application Mode? - Look to SPB16.2 and See!
By Gerald “Jerry” Grzenia on July 22, 2009
In prior releases, Allegro PCB Editor does not provide the user the ability to place or make placement changes easily More»
What’s Good About Cavity Support in APD? You’ll see for yourself using the SPB16.2 Release!
By Gerald “Jerry” Grzenia on July 29, 2009
No - we’re not talking teeth, candy, and cavities here...  More»