Cadence India eNewsletter

Cadence Low Power Solution Enables Fujitsu Microelectronics Tapeout of 65nm WiMAX Design
Trainings & Workshops
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Digital IC

Floorplanning, Physical Synthesis, Place and Route - V8.1
15 Jul 2009 - 17 Jul 2009,
Bangalore, India

Custom IC

Virtuoso Platform Update Training: Infrastructure; Analog & Physical Design - vIC6.1.3
13 Jul 2009 - 15 Jul 2009,
Bangalore, India

SKILL Language Programming-v5.1.41
21 Jul 2009 - 24 Jul 2009,
Bangalore, India

SKILL Programming for IC Layout Design-v5.1.41
27 Jul 2009 - 28 Jul 2009,
Bangalore, India

Advance Virtuoso Spectre Simulator-v6.1
03 Aug 2009 - 04 Aug 2009,
Bangalore, India


Basic SystemVerilog for Design and Verification - V8.1
27 Jul 2009 - 28 Jul 2009
Bangalore, India

Specman Elite Advanced Verification - v8.1
03 Aug 2009 - 06 Aug 2009,
Bangalore, India

Silicon Package Board

Allegro PCB Router-v16.01
23 Jul 2009 - 24 Jul 2009,
Bangalore, India

Allegro PCB SI Foundations-v16.2
06 Aug 2009 - 07 Aug 2009,
Bangalore, India

July 2009 
  Encounter Digital IC Platform News
Cadence: Committed to DFM
By Manoj Chacko on June 19, 2009.
On June 10, Cadence issued a press release that mentioned "…decreasing the level of investment in the manufacturing side of DFM" as part of restructuring activities. More»
Technical Webinars Hosted by the Experts – Don’t Miss Them!
By Soheil Modirzadeh on June 18, 2009.
Starting June 23, 2009, Cadence technical experts will host a series of technical webinars on myriad of topics. More»
  Virtuoso Custom IC Platform News
Fast and Accurate Sensitivity–Based–Multi–Corner Extraction
Girraj Khandelwal, Custom IC Technical Field Operations, Cadence Design Systems
Semiconductor process technology has been continually scaling down for the past four decades and the trend continues More»
Verilog-A Laplace Transform S–Domain Filters Application Note
The procedures described in this application note are deliberately broad and generic. Requirements for your specific design may dictate procedures slightly different from those described here. More»
  Incisive Verification Platform News
Fujitsu Microelectronics Solutions Adopts Cadence Verification Technology for Its Toughest Mixed–Signal Designs
FMSL Engineers Report Dramatically Improved Verification Results on Advanced Cell Phone Chip Design With Cadence Multi–Mode Simulation Suite. More»
Cadence and Xilinx Simplify SoC Development with Enterprise Verification Capabilities for FPGA Targeted Design Platforms
IEEE-Standard Encryption for SecureIP Models Offers 2X Performance Boost; Open Verification Methodology (OVM) to Increase Schedule Predictability and Quality. More»
  Allegro SPB Platform News
Hitachi Achieves 40% Reduction in PCB Place–and–Route Design Time With Cadence Global Route Environment
Hitachi’s Deployment of Allegro Global Route Environment Technology Significantly Streamlines PCB Design Process More»
What's Good About an FPGA Co–Design Environment? – Watch The Video For Answers
By Gerald Jerry Grzenia on June 24, 2009.
Check out Hemant Shah – Product Marketing Director for Allegro PCB Products – highlighting the new FPGA System Planner (FSP) product More»