Cadence India eNewsletter
Tagent and Cadence

Hosted Design Solutions Help Tagent Develop the First-Ever Antenna on Chip
Trainings & Workshops
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Digital IC

Logic Equivalence Checking with Encounter Conformal EC-v7.1
18 Jun 2009 - 19 Jun 2009,
Bangalore, India

Encounter RTL Compiler Basic Training -v8.1
12 Jun 2009 - 12 Jun 2009,
Bangalore, India

Custom IC

Virtuoso Platform Update Training: Infrastructure; Analog & Physical Design - vIC6.1.3
15 Jun 2009 - 17 Jun 2009,
Bangalore, India

Virtuoso Spectre Circuit Simulator - vMMSIM6.0br> 01 Jul 2009 - 03 Jul 2009,
Bangalore, India


Assertion-based Verification using SVA in the Incisive Formal Verifier
08 Jul 2009 - 08 Jul 2009,
Bangalore, India

Incisive Unified Simulator
25 Jun 2009 - 26 Jun 2009,
Bangalore, India

SVA-Incisive Simulation of PSL Assertions - V8.2
01 Jul 2009 - 01 Jul 2009,
Bangalore, India

Silicon Package Board

Allegro PCB Flow: Design Entry HDL Front-to-Back; Librarian & PCB Editor
22 Jun 2009 - 26 Jun 2009,
Bangalore, India

June 2009 
Cadence Unveils Integrated Chip Planning and Implementation Solution
  Encounter Digital IC Platform News
Cadence Encounter Digital IC Design Platform Adds 200 New Customers, including Ricoh and Siano
Companies Worldwide Select Encounter to Address Complex Design Closure, Low Power, Advanced Node, and Mixed Signal Design More»
NXP Semiconductors Accelerates Design Cycle using New Cadence Encounter Digital Implementation System for Industry’s First 45nm Digital TV Processor
Encounter’s Integrated Advanced Node Design–for–Manufacturing Capabilities Boosts Designer Productivity and Time–to–Market  More»
  Virtuoso Custom IC Platform News
Analog/Mixed Signal Routing Challenges in Sub–Nanometer Designs
Girraj Khandelwal, Custom IC Technical Field Operations, Cadence Design Systems
The IC industry is facing several design and manufacturing/yield related challenges as process geometries continue to shrink. More»
Application Notes on Direct Time-Domain Noise Analysis using Virtuoso Spectre
To assess the impact of device noise on circuit behavior, small signal approximation is most commonly used in commercial noise analysis tools. More»
  Incisive Verification Platform News
PLDA Achieves IP Success with Cadence SuperSpeed USB (USB 3.0) Verification IP
High–Quality Results and Predictable Time to Market Cited as Key Benefits More»
Cadence Speeds Systems Development with Automated Transaction-Level Verification
New SystemC Transaction Recording and Tracing Capabilities Eliminate Manual Steps for Modeling, Debugging and Analysis  More»
  Allegro SPB Platform News
Cadence Introduces Innovative FPGA-PCB Co-Design Solution
New Scalable Solution, Powered by Taray Technology, Can Shorten Design–In Time, Reduce End Product Cost and Mitigate Risk  More»
Successfully Designing FPGA–Based Systems
Nagesh Gupta, President and CEO, TARAY Inc.
FPGAs have come a long way since they were introduced in the 80s. The initial FPGAs were primarily used to create More»
Cadence Introduces Innovative FPGA-PCB Co-Design Solution
Generating excitement at CDNLive! EMEA in Munich, Cadence announced its new scalable FPGA–PCB co–design solution More»
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