Cadence India eNewsletter
Support & Training

As a startup in the highly competitive video processor chip business, it is critical that we get it right the first time. Cadence gave us the ability to quickly verify architecture and performance, and to work faster than traditional methods of prototyping while giving us greater confidence in the tapeout. More»
Trainings & Workshops
More Information»
Digital IC

Logic Equivalence Checking with Encounter Conformal EC-v7.1
21 May 2009 - 22 May 2009,
Bangalore, India

Basic SystemVerilog for Design and Verification - V8.1
21 May 2009 - 22 May 2009
Bangalore, India

Floorplanning, Physical Synthesis, Place and Route - V8.1
27 May 2009 - 29 May 2009
Bangalore, India

Signoff Timing Analysis with Encounter Timing System - v8.1
25 May 2009 - 26 May 2009,
Bangalore, India

Custom IC

Advance Virtuoso Spectre Simulator-v6.1
18 May 2009 - 19 May 2009
Bangalore, India

Virtuoso Platform Update Training: Infrastructure ; Analog & Physical Design - vIC6.1.3
25 May 2009 - 27 May 2009
Bangalore, India


SVA-Incisive Simulation of PSL Assertions - V8.2
11 May 2009 - 11 May 2009,
Bangalore, India

Basic SystemVerilog for Design and Verification - V8.1
21 May 2009 - 22 May 2009,
Bangalore, India

Specman Elite Advanced Verification - v8.1
25 May 2009 - 28 May 2009
Bangalore, India

May 2009 
Cadence Captures EDN Inovation Award
  Encounter Digital IC Platform News
VoltageStorm Is Alive and Kicking!
By Peter McCrorie on April 27, 2009
If your only news source were some of the common EDA pundits, you would likely believe that VoltageStorm is all but dead More»
WiMAX and the Road to Complete Independence From Network Cables: Sequans Communication’s Latest Innovation on WiMAX Devices
By Wei Tan on April 27, 2009
Step into any Starbucks hotspot or Wi-Fi cafe, and you’ll see something that was unthought-of just 10 years ago More»
  Virtuoso Custom IC Platform News
Spectre Turbo Circuit Simulator
By Irshad Alam, Custom IC Technical Field Operations,
Cadence Design Systems, India
With the process nodes shrinking down to 45nm and below, and as the design frequency continues to rise to several GHz introducing different types of parasitic effects More»
Jitter Measurements Using SpectreRF Application Note
Product Version MMSIM6.0
The procedures described in this application note are deliberately broad and generic. More»
Cadence and TSMC Introduce Mixed-Signal/RF Reference Design Kit in 65nm Process Technology
Collaboration Strengthens Mixed-Signal Ecosystem and Yields New Silicon-Proven PLL Noise-Sensitive Methodology for Faster Time to Market More»
  Incisive Verification Platform News
Performance-Aware e Coding Guidelines - Part 5
By Team Specman on April 28, 2009
In this last segment of the series on performance-aware coding, allow me to share with you two tips on improving the performance of Temporals. More»
Quick Tip - New Home For the "SVM" Docs
By Team Specman on April 24, 2009
FAQs: What happened to the "SVM" documentation, and to SVM in general? Has SVM been absorbed into OVM, or what?  More»
  Allegro SPB Platform News
What’s Good About Social Networking? Boomer Adoption up, Gen Y Flat
By Gerald "Jerry" Grzenia on April 22, 2009
I decided to switch gears a bit and write about an interesting article I read in Electronic Engineering Times More»
What’s Good About Relational Table Support in Capture-CIS? You’ll Need SPB16.2 to See!
By Gerald "Jerry" Grzenia on April 29, 2009
With SPB16.2 release, Capture-CIS allows you to create and use relational tables in the parts database. More»
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