Cadence India eNewsletter
Services
Services
Support & Training

In this edition, we will cover the benefits of our onsite training offerings and also will introduce to you to Onsite trainings; Advance with Engineer Explorer courses; Design Challenges and Design Foundation packages. More»
Trainings & Workshops
More Information»
Digital IC

Encounter RTL Compiler
Advance course -v8.1
16 Apr 2009 - 17 Apr 2009, Bangalore, India

Floorplanning, Physical
Synthesis,
Place and Route - V8.1
Apr 2009 - 22 Apr 2009,
Bangalore, India

Cadence Chip Optimizer
23 Apr 2009 - 24 Apr 2009,
Bangalore, India

Encounter Test JumpStart to ATPG - v7.2
30 Apr 2009,
Bangalore, India

Custom IC

Virtuoso Spectre Circuit Simulator - vMMSIM6.027 Apr 2009 - 29 Apr 2009, Bangalore, India

Virtuoso Platform Update Training: Infrastructure ; Analog & Physical Design - vIC6.1.3
20 Apr 2009 - 22 Apr 2009, Bangalore, India

Verification

Advance SystemVerilog Language and Application - v8.1
20 Apr 2009 - 24 Apr 2009,
Bangalore, India

Assertion-based Verification using SVA in the Incisive Formal Verifier
17 Apr 2009 - 17 Apr 2009,
Bangalore, India

Incisive Comprehensive Coverage-v8.1
30 Apr 2009 - 30 Apr 2009,
Bangalore, India

April 2009 
Cadence Captures EDN Inovation Award
  Encounter Digital IC Platform News
Global Unichip Announces Greater Than 3X Schedule Reduction of Full-Chip Design Closure on 50M Gate Design with New Encounter Digital Implementation System
Silicon Predictability, Complete Multi-Mode/Multi-Corner Analysis, and Embedded Timing Signoff and Signal Integrity Drive Rapid Design Closure More»
Cadence and NEC Electronics Announce Encounter Digital Implementation System To Support NEC Electronics’ System LSI with Built-In V850 CPU Core
NEC Electronics Achieves 50 Percent Reduction in Design Turnaround Time for Leading-Edge System LSI More»
  Virtuoso Custom IC Platform News
CMP Aware RC Extraction
Jagadeesan J, Lead Application engineer, Cadence Design Systems, Inc.
The number of transistors per chip doubles every 18 months, at no cost to customers* and this is achieved through technology scaling More»
How To
Encounter-Virtuoso Mixed Signal Floorplanning and Physical Implementation Flow
Solution Flow Name: Encounter-Virtuoso Mixed Signal Floorplanning and Physical Implementation Flow - Big designs with large number of blocks More»
  Incisive Verification Platform News
Tech Tip: Determining When a Sequence Has Finished
By Team Specman on March 12, 2009 
Imagine the complex scenario whereby you start the *same* sequence on multiple sub-drivers. Naturally each started sequence has its own execution thread More»
New eDocs Makes Documenting Fun!
By Team Specman on March 13, 2009
Documentation. This single word tends to sends shivers up the spine of many an engineer. People like to code  More»
  Allegro SPB Platform News
What’s Good About Allegro® Design Entry HDL - User Customizations? You Tell Me!
By Gerald "Jerry" Grzenia on March 11, 2009
Well... if you like tweaking and tuning an environment to suit your needs, Allegro Design Entry HDL (DEHDL or previously known as ConceptHDL) has plenty to offer.  More»
It’s All In The Metrics
By Matthew Bromley on March 18, 2009
You could be forgiven for thinking that this was going to be a discussion of the benefits of imperial versus metric units More»
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