Cadence India eNewsletter
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Benefits of Standard / tailored / Custom training was already described in the last edition. In this edition we would like to introduce you to two of our offerings - Internet Learning Series (iLS) & Virtual Classroom.  More»
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March 2009 
  Encounter Digital IC Platform News
Turning the Downturn Upside Down
By Chi-Ping Hsu on February 20, 2009
Many bemoan the gloom and doom of the present economic situation, and it is true that some have been really hurt by it.  More»
Demo: Automatic Floorplan Synthesis in Encounter
By Robert Dwyer on February 26, 2009
As an Applications Engineer, the first demonstrations you deliver of a new technology are always the most interesting. More»
  Virtuoso Custom IC Platform News
Custom Layout Migration and DFM Optimization using Virtuoso Layout Migrate (VLM)
Vishal Agarwal, Lead Application Engineer, Cadence Design Systems, India
In this competitive world, quality of product and time to market are essential for growth of any semiconductor company More»
Real Valued Modeling for Mixed Signal Simulation
Walter Hartong and Scott Cranston
Real Valued Modeling (RVM) is a way by which users can perform verification of their analog or mixed-signal designs  More»
  Incisive Verification Platform News
OVM Extended to Efficiently Manage Coverage Metrics
Mentor Graphics and Cadence Design Systems, Inc. today announced they have extended the Open Verification Methodology (OVM) to include the Unified Coverage Database More»
AMD Selects Cadence Incisive Palladium Series To Verify Complex Graphics Design
Cadence Accelerator/Emulator Addresses System-level Verification Complexity and Speeds Delivery of First Silicon Success for ATI RadeonTM HD 4800 Series First Silicon More»
Cadence Incisive Verification IP Portfolio Delivers ’All-in-One’ Flexibility and Higher Value for SoC Developers
Portfolio Offers OVM Multi-Language Support with Metric-Driven and Assertion-Based VIP Under a Single License More»
  Allegro SPB Platform News
What’s Good About FPGA Capabilities in Capture? Download the SPB16.2 Release and See!
By Gerald "Jerry" Grzenia on February 18, 2009
In recent years, the design of FPGA and Printed Circuit Boards (PCBs) has become increasingly parallelized as opposed to the traditional sequential model. More»
Designing DDR3 Interfaces In a Constraint Driven Design Environment
By Brad Griffin on February 24, 2009
If you’ve been wondering how to capture high speed memory interface design intent early in your design process and drive that through to final verification More»
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