Cadence India eNewsletter
Services
Talent Development
To reduce risk, improve project productivity, and achieve overall quality goals, design teams need the right set of skills appropriate for each stage of the design and verification process More»
Trainings & Workshops
More Information»
Digital IC
Encounter Test JumpStart to ATPG; Version 6.2.1
November 27, 2008
Cadence, Bangalore
SOC Encounter
Dec 1, 2008 - Dec 3, 2008
Cadence, Bangalore
Logic Equivalence Checking with Encounter Conformal: Basic & Advanced: Version 7.1
Dec 10, 2008 - Dec 11, 2008
Cadence, Bangalore
Custom IC
SKILL Language Programming; Version 5.1.41
Nov 11, 2008 - Nov 14, 2008
Cadence, Bangalore
SKILL for IC Layout Design; Version 5.1.41
Nov 17, 2008 - Nov 18, 2008
Cadence, Bangalore
AMS Designer; Version 5.7
Dec 4, 2008 - Dec 5, 2008
Cadence, Bangalore
Silicon Package Board
Allegro PCB Power Integrity ; Version 15.7
December 12, 2008
Cadence, Bangalore
Verification
Specman Elite Basics for Verification Environment Users
Nov 3, 2008 - Nov 5, 2008
Cadence, Bangalore
Incisive Simulator Assertion Based Verification (ABV) Using SVA
Nov 6, 2008 - Nov 7, 2008
Cadence, Bangalore
Basic SystemVerilog Language
Nov 10, 2008 - Nov 11, 2008
Cadence, Bangalore
November 2008 
  Encounter Digital IC Platform
Moai Electronics Accelerates Flash Memory Controller Tapeout with Cadence Logic Synthesis and DFT Solutions
HSINCHU, Taiwan, 29 Oct 2008 More»
Cadence Low-Power Solution Enables Legend Silicon to Achieve 90nm First Silicon Success
Legend selects Cadence as primary EDA supplier, Leverages Low-Power Solution for advanced DTV and Wireless Design More»
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  Custom IC
Grace Semiconductor Adopts Cadence Virtuoso 6.1 PDK Development System
Leading Foundry Efficiently Develops and Tests Process Design Kits for Analog, Mixed-Signal, RF and Custom IC Design More»
CMP Aware RC Extraction
Jagadeesan J, Lead Application engineer, Cadence Design Systems, Inc. More»
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  Functional Verification
Cadence Expands Portfolio of System-Level Verification IP and SpeedBridge Adapters to Boost Acceleration and Emulation Performance
The New System VIP and SpeedBridge Adapters Speed Up Time to Market and Improve Quality, Further Extending Cadence Leadership in VIP Portfolio Breadth and Depth More»
OVM - The "O" Means Opportunity
By Adam Sherer on October 31, 2008 More»
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  Silicon Package Board Platform
What’s Good About Directive Locking?
By Gerald "Jerry" Grzenia on October 29, 2008  More»
What’s Good about the new "Class" Scope for Match Groups in Constraint Manager?
By Gerald "Jerry" Grzenia on October 8, 2008 More»
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