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Dear Readers,

We are pleased to announce the launch of C to Silicon Compiler, a high–level synthesis product that improves designer productivity up to 10 times in creating and re–using system–on–chip IP. The innovative technology in C–to–Silicon Compiler helps bridge the gap between register transfer level (RTL) models–commonly used to verify, implement, and integrate SoCs–and system–level models, usually written in C/C++ and SystemC.

The Power Forward Initiative continues to gain momentum with three Japanese design services companies – NIPPON SYSTEMWARE CO., LTD. (NSW), Dai Nippon Printing Co., Ltd. (DNP) and Toppan Technical Design Center Co., Ltd. – recently joining the initiative and are offering Common Power Format (CPF)–enabled low-power design capabilities to their design services customers. With the addition of these three leading Japanese design centers the PFI increases its membership to over 30 companies around the world, representing a broad spectrum of IC design, IP, service and manufacturing providers.

Read more about these two announcements in this newsletter.

Rahul Arya
Marketing Director

Tool Automates Engineering-Change-Order Generation

Almost all chip designs go through engineering change orders (ECOs) to implement late-stage design modifications due to changes in design requirements or incorrect logic function. More»

On-Chip Thermal Analysis Is Becoming Mandatory

Accounting for on-chip thermal effects, which are already a problem at 65 nm, will become a requirement when implementing 45- and 32-nm technologies. More»

Cadence Expands System-Level Offerings with Introduction of C-to-Silicon Compiler

SAN JOSE, Calif., 14 Jul 2008

New Solution Increases Designer Productivity Up to 10X in IP Creation and Re-Use More»

Cadence Delivers OVM-Compliant Verification IP

SAN JOSE, Calif., Jun 09, 2008

Cadence Verification IP Enables Open Verification Methodology (OVM) Users to Automate Protocol Verification and Compliance to Meet Schedule Demands. More»

New standards effort targets verification IP interoperability

By Richard Goering
04/28/08

The Accellera standards organization has launched a verification IP (VIP) technical subcommittee that will seek to define a standard methodology to allow VIP interoperability and reuse, More»

Cadence Virtuoso Spectre with Turbo Technology Adopted by National Semiconductor

SAN JOSE, Calif., Jun 16, 2008

National Realizes up to 6X Performance Gains in Verifying Complex Analog Designs More»

The New, Simplified AMS Designer Virtuoso Use-Model

Vivek Astvansh, Member of Consulting Staff, Cadence Design Systems (I) Pvt Ltd.

This article is meant for users of the AMS Designer Virtuoso Use-Model (AVUM). We discuss the recent improvements done to the OSS-based Verilog-AMS Netlister More»

Virtuoso Layout Suite IC 6.1 (Part 1)

By Colin Sutlieff and Robert Schweiger

To meet consumer demand for new features and more functionality packed into ever smaller electronics devices, companies are turning to full-custom design. More»

Methodology and Flow Challenges in System-level Co-design of Multi-die Packaged Systems

Keith Felton - Cadence Design Systems

Today’s designs require flows with concurrent capabilities that bridge the communication gap between the IC, Package, and PCB environments More»