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Digital IC

Logic Equivalence Checking with Encounter Conformal : Basic & Advanced : Version 7.1
June 17, 2008 - June 18, 2008 Cadence

Encounter Test JumpStart to ATPG ; Version 6.2.1
July 2, 2008

SOC Encounter
July 16, 2008 - July 18, 2008

Custom IC

Advance Spectre ; Version 6.2
June 19, 2008 - June 20, 2008

Virtuoso XL Layout Editor ; Version 5.1.41
July 7, 2008 - July 9, 2008

Silicon Package Board

Allegro PCB Flow : HDL Front to Back ; PCB Librarian & PCB Editor
June 23, 2008 - June 27, 2008

Allegro PCB Router Basics ; Version 16.0
July 24, 2008 - July 25, 2008


SystemVerilog Language and Application : Advance
June 16, 2008 - June 20, 2008

Specman Elite Basics for Verification Environment Users
June 23, 2008 - June 25, 2008

Incisive Simulator Assertion Based Verification (ABV) Using SVA
June 26, 2008 - June 27, 2008

Assertion-based verification using PSL in the Incisive formal verifier
July 28, 2008 - July 29, 2008

Specman Elite Basics for Verification Environment Users
July 30, 2008 - August 1, 2008

We’d like to hear your comments or questions about this newsletter. Email us»

Greetings from Cadence!

The Power Forward Initiative is growing from strength to strength. Last month, we announced that MindTree had joined the initiative; this month, we are pleased to welcome VeriSilicon into the PFI.

Not long ago, Cadence’s Michael Tian gave Cadence users a sneak preview of the newly released Cadence® Virtuoso® Multi-Mode Simulation 7.0. Read on for the excerpts of the interview. And more for custom IC users - Steve Lewis’s article talks about the key features in the Virtuoso 6.13 release.

Best wishes,

Rahul Arya
Marketing Director
    Cadence Encounter Digital IC Platform News
Renesas Adopts Cadence SoC Encounter for Large Scale Complex Chips and Flip-Chip Design
San Jose, Calif., May 12, 2008
Renesas Gains Productivity, Cost, and Time-to-Market Advantages With Cadence SoC Encounter  More»
    Cadence Incisive Verification Platform News
DAC Event Connects Users in the OVM World Community
San Jose, Calif., and Wilsonville, Ore., Jun 05, 2008
First Open Verification Methodology (OVM) World Summit to Be Held at Design Automation Conference More»
    Cadence Virtuoso Custom IC Platform News
Interview: Turbo Technology speeds analog simulation, preserves accuracy
April 28, 2008, Michael Tian - Cadence Design Systems
Cadence® Virtuoso® Multi-Mode Simulation 7.0 was released on April 10, 2008. cdnusers talked to Michael Tian, engineering director of the Virtuoso Spectre R&D team  More»
Interview: Key Features in Virtuoso 6.13 Release
April 28, 2008, Steve Lewis - Cadence Design Systems
The Virtuoso 6.1.3 release integrates the Cadence space-based router into the Virtuoso Cockpit to help users work more easily with sub-90nm design.  More»
Virtuoso Schematic Editor
By Carsten Deinstrop and Robert Schweiger
Opposed to digital design in full, custom design starts with schematic entry. Especially for complex ICs this could be a quite tedious and lengthy task. Things like quick navigation within complex hierarchical designs,  More»
Virtuoso Analog Design Environment XL
By Walter Hartong and Robert Schweiger
The IC industry is integrating more and more features onto one single chip. Needless to say, specifi cations of these chips are getting quite complex. Unfortunately, design projects have to be completed within the same or less time, requiring more efficient design methodologies  More»
    Cadence Allegro SPB Platform News
Global Route Environment Technology for Allegro PCB Design GXL
Global Route Environment technology for Cadence® Allegro® PCB Design GXL sets the new standard in PCB design and layout. For the first time, PCB designers have an automated methodology More»