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  Trainings & Workshops
Digital IC

Logic Equivalence Checking with Encounter Conformal
Basic & Advanced:
Version 7.1
June 17, 2008 - June 18, 2008

Encounter Test JumpStart to ATPG; Version 6.2.1
July 2, 2008

SOC Encounter July 16, 2008 - July 18, 2008

Custom IC

AMS Designer; Version 5.7
June 9, 2008 - June 10, 2008

Advance Spectre; Version 6.2
June 19, 2008 - June 20, 2008

Virtuoso XL Layout Editor; Version 5.1.41
July 7, 2008 - July 9, 2008

Silicon Package Board

Allegro PCB SI Foundations; Version 16.0
June 5, 2008 - June 6, 2008

Allegro PCB Flow: HDL Front to Back; PCB Librarian & PCB Editor
June 23, 2008 - June 27, 2008

Allegro PCB Router Basics; Version 16.0
July 24, 2008 - July 25, 2008


Assertion-based Verification using SVA in the Incisive Formal Verifier
May 22, 2008 - May 23, 2008

SystemVerilog Language and Application: Advance
June 16, 2008 - June 20, 2008

Specman Elite Basics for Verification Environment Users
June 23, 2008 - June 25, 2008

Incisive Simulator Assertion Based Verification (ABV) Using SVA
June 26, 2008 - June 27, 2008

Assertion-based verification using PSL in the Incisive Formal Verifier
July 28, 2008 - July 29, 2008

Specman Elite Basics for Verification Environment Users
July 30, 2008 - August 1, 2008

We’d like to hear your comments or questions about this newsletter. Email us»

Dear Readers,
Technology on Tour 2008 took place in Delhi and Hyderabad in May. We had a great turnout in both locations, where customers learnt about Low Power, Advanced Node design, Advanced Verification and Silicon Package Board design.
There are two important announcements this month:
First, MindTree Consulting has joined the Power Forward Initiative and will be offering a Common Power Format (CPF)-enabled low-power flow to its design services customers. With the addition of MindTree, the PFI continues to increase its momentum and now has 27 members.
Second, Cosmic Circuits has joined the Cadence OpenChoice Program, augmenting the Program with its rich portfolio of differentiated Analog IP-cores for A/D and D/A conversion, WiFi and WiMax Analog-Baseband solutions, Power-Management, Analog Audio solutions, Clocking and Interface that work optimally on Cadence flows.
Both these announcements demonstrate that Cadence not only provides complementary design and verification capabilities but also facilitates open interoperability and optimized handoffs throughout the entire silicon design chain.
Best wishes,

Rahul Arya
Marketing Director

    Cadence Encounter Digital IC Platform News
TTM, Inc. adopts Cadence Holistic DFM Solutions for 65nm and Below Designs
SAN JOSE, Calif., April 22, 2008
Cadence SoC Encounter and Litho Physical Analyzer Optimize Yields and Improve Manufacturability. More»
IDT uses Cadence Encounter Conformal Constraint Designer to accelerate time to market
SAN JOSE, Calif., April 15, 2008
IDT Cites Productivity, Predictability and Performance Advantages. More»
STARC Adopts Cadence Encounter Timing System as its Static Timing Analysis Signoff Solution
SAN JOSE, Calif., April 7, 2008
PRIDE V2.0 Reference Flow Incorporates Cadence Encounter Timing System for Advanced Node Design. More»
Seiko NPC Sees a Big Productivity Boost in DFT Design Flow with Integrated Cadence Test and Synthesis Technologies
SAN JOSE, Calif., April 7, 2008
Seiko NPC Successfully Implements Complex Design using New Design-for-Test Functionality in Cadence Encounter Test and Encounter RTL Compiler. More»
    Cadence Incisive Verification Platform News
How floorplanning guides synthesis and physical design
By Jack Erickson, Cadence Design Systems
Modeling interconnect delay during synthesis has always presented a "chicken-and-egg" problem. Synthesis creates logic structures to meet timing goals. More»
    Cadence Virtuoso Custom IC Platform News
Cadence Strengthens Advanced Node Design Solutions with New Production-Proven Enhancements for Custom IC Design
CDNLive! EMEA 2008, MUNICH, April 29, 2008
Virtuoso Custom Design Platform Delivers Improved Performance and Concurrent Manufacturability Solutions. More»
Spectre Turbo Circuit Simulator
Irshad Alam, Custom IC Technical Field Operations,Cadence Design Systems,India
With the process nodes shrinking down to 45nm and below, and as the design frequency continues to rise to several GHz introducing differentypes of parasitic effects that may cause re-spins. More»
New Cadence Technology Speeds Analog and Mixed-signal Verification
CDNLive! EMEA 2008, MUNICH, April 29, 2008
Enhanced Virtuoso Spectre Circuit Simulator with 'Turbo' Technology Boosts Performance with Full SPICE Accuracy. More»
    Cadence Allegro SPB Platform News
Methodology and Flow Challenges in System-level Co-design of Multi-die Packaged Systems
April 29, 2008, Keith Felton - Cadence Design Systems
Today’s designs require flows with concurrent capabilities that bridge the communication gap between the IC, Package, and PCB environments More»
Cadence Delivers Silicon-Ready Reference Methodologies for ARM Cortex-A9 Processor
SAN JOSE, Calif., April 29, 2008
Silicon-Ready Flow for Next-Generation Low-Power Devices Performance-Proven to 800MHz. More»