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Digital IC

SOC Encounter
April 23, 2008 - April 25, 2008
Cadence, Bangalore

Encounter RTL Compiler; Version 7.1
May 6, 2008
Cadence, Bangalore

Custom IC

Virtuoso XL Layout Editor; Version 5.1.41
April 14, 2008 - April 16, 2008
Cadence, Bangalore

SKILL Language Programming; Version 5.1.41
May 13, 2008 - May 16, 2008
Cadence, Bangalore

SKILL for IC Layout Design; Version 5.1.41
May 19, 2008 - May 20, 2008
Cadence, Bangalore

Silicon Package Board

Allegro PCB SI Foundations; Version 16.0
May 22, 2008 - May 23, 2008
Cadence, Bangalore

Verification

Specman Elite Basics for Verification Environment
Users
April 14, 2008 - April 16, 2008
Cadence, Bangalore

Basic SystemVerilog Language
April 17, 2008 - April 18, 2008
Cadence, Bangalore

Incisive Simulator Assertion Based Verification (ABV) Using PSL
April 21, 2008 - April 22, 2008
Cadence, Bangalore

Basic SystemVerilog Language
May 12, 2008 - May 13, 2008
Cadence, Bangalore

Specman Elite Advance Course
May 19, 2008 - May 21, 2008
Cadence, Bangalore

Assertion-based verification using SVA in the Incisive formal verifier
May 22, 2008 - May 23, 2008
Cadence, Bangalore.

We’d like to hear your comments or questions about this newsletter. Email us»

Greetings from Cadence!

The Power Forward Initiative (PFI) has just released "A Practical Guide to Low-Power Design - User experience with CPF." Available for free download, this guide captures thousands of hours of actual design experience from many of the 26 PFI-member companies.

Also this month, don’t miss the Call for Papers for CDNLive! India 2008. CDNLive! presents a great opportunity to share your expertise, network with your peers from the industry and exchange tips & tricks. All those who submit an abstract by May 1 will be in a draw to win an Apple iPod nano. So don’t delay!

Best wishes

Rahul Arya
Marketing Director
    Cadence Encounter Digital IC Platform News
Cadence Acquires Chip Estimate, Extending Solutions to Improve Decision-Making at Early Stages of IC Planning
SAN JOSE, Calif., March 11, 2008
Electronics Industry to Benefit from Minimized Risk and Cost of Designing Today’s Complex Chips More»
Cadence Encounter Conformal ECO Designer Improves Logic Designers’ Productivity
SAN JOSE, Calif., March 25, 2008
New EDA Offering Automates Functional Engineering Change Order (ECO) Implementation Process More»
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    Cadence Incisive Verification Platform News
Interview: Verification Planning and Management Methodology Focuses on All the Right Things
March 24, 2008, Ze’ev Shtadler - Cadence Design Systems
Verification Planning and Management is rapidly becoming accepted as an important technical discipline for advanced designs. More»
Sunplus Selects Cadence Incisive Xtreme to Meet Faster Time to Market by Achieving Orders of Magnitude Performance Gain in Simulation Acceleration
HSINCHU, Taiwan, March 21, 2008
Incisive Xtreme Server Offers Acceleration Performance of up to 1000x Over Traditional Simulation Methods, Enabling Sunplus to Complete the Verification Tasks Within Tapeout Schedule More»
PLX Technology Adopts Cadence Incisive Palladium II Accelerator/Emulator for Full System Verification
SAN JOSE, Calif., April 2, 2008
Easy Deployment, Early "Bug" Detection and Robust Portfolio of Verification IP Improve Product Quality and Schedule Predictability More»
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    Cadence Virtuoso Custom IC Platform News
Litho Aware Device and Interconnect Extraction
Brajesh Heda, Lead App. Engineer, Cadence Design Systems, India
Designers have started facing heat due to manufacturing variations in sub 90nm process technologies, which are not in their control. It’s mainly due to limitations in manufacturing equipment area. More»
What is New in AMSDesigner/AMS-Ultra in IUS6.11?
By Ramkumar Madhavan, Lead Support AE, Cadence Design Systems
There are 2 major flows in AMSDesigner. AMSD Virtuoso Flow (Gui Based) and AMSD Incisive Flow (Command line based). There are many major enhancements being made in both the flows in IUS6.11 release for AMS Designer. More»
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    Cadence Allegro SPB Platform News
Challenges in Implementing DDR3 Memory Interface on PCB Systems
March 11, 2008, Phil Murray - Altera Corporation and Feras Al-Hawari,
Cadence Design Systems
Covers modeling, simulation, and physical layout approaches required to meet JEDEC-defined termination and tight timing requirements for designing DDR3 memory interfaces on PCB systems. More»
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