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  Trainings & Workshops
Digital IC

Voltage Storm Power Rail Analysis
March 18, 2008 - March 20, 2008

Encounter Test Jumpstart to ATPG ; Version 6.2.1
April 10, 2008

SOC Encounter
April 23, 2008 - April 25, 2008

Custom IC

Advance Spectre ; Version 6.2
March 24, 2008 - March 25, 2008

Virtuoso XL Layout Editor ; Version 5.1.41
April 14, 2008 - April 16, 2008

Silicon Package Board

Allegro PCB SI Foundations; Version 16.0
March 27, 2008 - March 28, 2008


Verification

Basic SystemVerilog Language
March 27, 2008 - March 28, 2008

Assertion-based verification using PSL in the Incisive formal verifier
March 31, 2008 - April 1, 2008

Specman Elite Basics for Verification Environment Users
April 2, 2008 - April 4, 2008

Basic SystemVerilog Language
April 17, 2008 - April 18, 2008

Incisive Simulator Assertion Based Verification (ABV) Using PSL
April 21, 2008 - April 22, 2008
  Feedback
We’d like to hear your comments or questions about this newsletter. Email us»


Greetings from Cadence!

I am delighted to announce that Cadence has bagged the prestigious DesignVision Award by International Engineering Consortium (IEC), for its innovative Cadence Litho Electrical Analyzer. Also, the Open Verification Methodology (OVM), developed jointly by Cadence and Mentor Graphics, has also been recognized with a DesignVision award.

Those of you who attended CDNLive! India 2007 will remember that we launched Cadence Engineering Services, a collaboration infrastructure that enables greater efficiency and faster turnaround during all phases of a project. This issue has more information about Cadence Services and how it can help your company accelerate productivity.

Best wishes and happy reading!

Rahul Arya
Marketing Director
    Cadence Encounter Digital IC Platform News
Using Cadence Chip Optimizer with SoC Encounter GXL for Design Closure
March 5, 2008, Narayanan Thondugulam - P.A. Semi
Describes the use of Cadence Chip Optimizer for design closure in conjunction with SoC Encounter GXL-based place-and-route flows. More»
Cadence Litho Electrical Analyzer Wins Prestigious DesignVision Award
Cadence IC Design Solution Enables the IC Industry to Continue Electronics Design at the Leading Edge.

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, has been distinguished by the International Engineering Consortium (IEC) with a 2008 DesignVision Award for Product of the Years. More»
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    Cadence Incisive Verification Platform News
Interview: Coverage-driven Random Verification
February 7, 2008, Apurva Kalia - Cadence Design Systems
Coverage-driven random verification methods are supported in the Cadence® Incisive 6.2 software release. Apurva discusses how to take advantage of this solution More»
Parallel and Modular Flows over a Basic Chip Level Environment
March 5, 2008, Shlomi Sperber - Texas Instruments, Israel
Describes Parallel and Modular flows used in making various products More»
Cadence Design Systems and Mentor Graphics Win DesignVision Award for Open Verification Methodology
Cadence Design Systems, Inc. (NASDAQ: CDNS) and Mentor Graphics Corp. (NASDAQ: MENT) has announced that the Open Verification Methodology (OVM), developed jointly by the two companies, was awarded the Best Design Verification Tool DesignVision; More»
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    Cadence Virtuoso Custom IC Platform News
Model-Based Verification and Analysis for 65/45nm Physical Design
February 27, 2008, Jason Hibbeler, Daniel N. Maynard, Sarah C. Braasch - IBM

IBM and Cadence are developing a software infrastructure combining MRD checking and yield simulation, allowing for flexible integration of different (including third-party) simulators. More»
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    Cadence Allegro SPB Platform News
Cadence Signal Integrity for Double Data Rate Interface
February 12, 2008, Prithi Ramakrishnan - Motorola, Ken Willis - Cadence Design Systems

Discuss the use of Allegro PCB SI in the design and analysis of a processor-memory interface in one of Motorola’s products. More»
A Fresh Approach to Serdes I/O Modeling
February 7, 2008, Hemant Shah - Cadence Design Systems

Describes the need for algorithmic models, the interoperability problem, the need for IBIS BIRD 104 and the benefits systems companies and SERDES IP companies will derive from this new approach. More»
Using mm.pl to Create DML MacroModels for Use in Channel Analysis
February 27, 2008, Andy Haas - Cadence Design Systems

An updated appnote/tutorial with example models and ready-to-simulate topologies.Includes compatibility with additional buffer types and document revisions for SPB16.01 More»
Accent Uses Cadence Low-Power Solution for Fast, Accurate Tapeout of Low-Power Production Design
CPF-Enabled Flow Results In On-Time Tapeout of Complex Low-Power RFID Application Design More»
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