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Digital IC

SOC Encounter
February 27, 2008 - February 29, 2008

Logic Equivalence Checking with Encounter Conformal: Basic & Advanced: Version 7.1
March 6, 2008 - March 7, 2008

Voltage Storm Power Rail Analysis
March 18, 2008 - March 20, 2008

Custom IC

SKILL for IC Layout Design; Version 5.1.41
February 18, 2008 - February 19, 2008

AMS Designer; Version 5.7
March 3, 2008 - March 4, 2008

Advance Spectre; Version 6.2
March 24, 2008 - March 25, 2008

Silicon Package Board

Allegro PCB Flow: HDL Front to Back; PCB Librarian & PCB Editor
February 18, 2008 - February 22, 2008

Allegro PCB SI Foundations; Version 16.0
March 27, 2008 - March 28, 2008

Allegro PCB SI Foundations; Version 16.0
May 22, 2008 - May 23, 2008

Allegro PCB Flow: HDL Front to Back; PCB Librarian & PCB Editor
June 23, 2008 - June 27, 2008


Specman Elite Advanced Course
February 18, 2008 - February 20, 2008

Assertion-based verification using SVA in the Incisive formal verifier
February 21, 2008 - February 22, 2008

Specman Elite Basics for Verification Environment Users
March 10, 2008 - March 12, 2008

Incisive Simulator Assertion Based Verification (ABV) Using SVA
March 13, 2008 - March 14, 2008
We’d like to hear your comments or questions about this newsletter. Email us»

Greetings from Cadence!

Cadence® Virtuoso® Multi-Mode Simulation combines the industry’s leading simulation engines to deliver a complete design and verification solution. It meets the changing simulation needs of designers as they move through the design cycle, from architecture exploration to block-level development to RF design and to final full-chip verification. It is a comprehensive design and verification solution that combines the industry’s leading SPICE, FastSPICE, RF, and mixed-signal simulators in a unique shared licensing. In this issue, read Sr Services AE Badrinarayan Zanwar’s article on what's new in MMSIM6.2.

Also in this issue are two other articles in the Custom IC domain written specially for this e-newsletter; one on sensitivity-based multi-corner extaction by Girraj Khandelwal, Application Engineer, and another on Virtuoso RF Designer for RFIC designs by the Virtuoso RF Designer team.

Best wishes and happy reading!

Rahul Arya
Marketing Director
    Cadence Encounter Digital IC Platform News
Learn to Optimize Your Low Power Design Process
January 4, 2008, Neil Hand - Cadence Design Systems
ECN Design Network, which features ideas, tips, and tutorials for the electronic design professional, is featuring a series of tutorials on low power design to address an issue of interest to many of its readers. More»
STARC Releases ’PRIDE’ Reference Design Flow Using Cadence Low-Power and DFM Solutions
PRIDE V1.5 Reference Flow Incorporates CPF-based Low-Power Solution and Cadence DFM Technologies for Advanced Node Designs. More»
    Cadence Incisive Verification Platform News
Interview: By Popular Demand-SystemVerilog Open Verification Methodology
January 10, 2008, Tom Anderson - Cadence Design Systems
This week, Cadence and Mentor Graphics announced that the new Open Verification Methodology for SystemVerilog is available for download. More»
    Cadence Virtuoso Custom IC Platform News
What's new in MMSIM6.2 ?
By Badri Narayan Zanwar
MMSIM is continuously updated to incorporate new features. Many new enhancements have been made in MMSIM6.2 for Spectre and Ultrasim which has further increased its usability. More»
Fast and Accurate Sensitivity-Based-Multi-Corner Extraction
Girraj Khandelwal, Custom IC Technical Field Operations, Cadence Design Systems
Semiconductor process technology has been continually scaling down for the past four decades and the trend continues. More»

Interview: Virtuoso Passive Component Designer Now Supports Synthesis for Customer Pcells
Bo Wan, Cadence Design Systems
Virtuoso Passive Component Designer provides a complete flow for the design, analysis and modeling of inductors, transformers and transmission lines. In this cdnusers interview, Bo Wan, VPCD Engineering Manager, briefly discusses the most important features. More»
Toshiba Collaborates with Cadence to Improve Analog and Mixed-Signal Design Reliability at 65nm and Below
Toshiba Adopts Cadence Virtuoso UltraSim Full-Chip Simulator for Reliability Analysis Flow. More»
    Cadence Allegro SPB Platform News
Comparison of Signaling and Equalization Schemes in High Speed SerDes (10-25Gbps)
Dr. Cathy Ye Liu, LSI Logic
Dr. Joe Caroselli, Telegent Systems
In this paper, performance of a wide variety of signaling and equalization schemes in the SerDes system are compared. More»
Congratulations to the winners of the January 2008
Sourcelink promotion!

   Prasanna Misra
Indian Institute Of Technology
   Arijit Dutta
Freescale Semiconductor
   Pawan Gandhi
Freescale Semiconductor
   Neha Chawla
   Varun Sukumaran
   Atul Ware
Conexant Systems
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