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Virtuoso XL
January 23, 2008 - January 25, 2008
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Cadence Bangalore Office

Basic Skill Training
February 12, 2008 - February 15, 2008
Training Room 1
Cadence Bangalore Office

Skill for IC Layout
February 18, 2008 - February 19, 2008
Training Room 1
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AMS Designer
March 3, 2008 -
March 4, 2008
Training Room 1
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Advance Spectre
March 24, 2008 -
March 25, 2008
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Greetings from Cadence!

Welcome back and happy New Year! In this issue, Raj Gutta from Cadence Global Customer Care team has written a useful article on Sourcelink, the web resource for Cadence customers. Whether you need to create an account or troubleshoot, you will find answers to all your questions in this article.

Also in this issue, we bring you the first in a series of webinars featuring presentations from CDNLive! for Custom IC Designers. Watch this space for more updates.

If you have any articles to contribute, please write to us at communications_india@cadence.com.

Best wishes

Rahul Arya
Marketing Director
    Cadence Encounter Digital IC Platform News
Motivations And Methodology For Nanometer Library Characterization
Libraries provide the foundation for digital design implementation. Consequently, any inaccuracy in library creation will permeate throughout the design flow for every chip that uses that library. More»
    Cadence Incisive Verification Platform News
Interview: Closing in on Profitability with Leading-Edge Verification Practices
December 5, 2007, Erik Panu - Cadence Design Systems
cdnusers talked to Cadence Engineering Group Directors Mike Stellfox and Erik Panu to find out when and how to deploy the Incisive® Plan-to-Closure Methodology. More»
Incisive transaction-based acceleration 2.0
Part of Incisive® acceleration and emulation technology, the next generation of transaction-based acceleration-TBA 2.0-reduces verification time More»
Award-Winning Interoperable SystemVerilog Methodology Ready for Download
"Cadence and Mentor Announce Immediate Availability of the Open Verification Methodology."  More»
    Cadence Virtuoso Custom IC Platform News
Inductor Design Flow
January 7, 2008, Dr.-Ing. Krzysztof Kitlinski - Infineon Technologies AG
Describes the Infineon created Inductor Design Flow applied in several successful VCO designs to create symmetrical and asymmetrical inductors.  More»
Webinar: Using Virtuoso Spectre RF Noise-Aware PLL Methodology to Predict PLL Behavior Accurately
December 5, 2007, Helene Thibieroz - Cadence Design Systems
Webinar: first in a series of webinars for Custom IC Designers featuring presentations from CDNLive! More»
UMC Foundry Design Kit for New Cadence Virtuoso Platform Speeds Production of 65nm designs.
Performance and Productivity Features of Latest Virtuoso Platform Now Supported by UMC’s 65nm FDKs. More»
Virtuoso Passive Component Designer
Integral part in Infineon’s "Inductor on Demand" Design Flow.  More»
    Cadence Allegro SPB Platform News
Webinar: Using Cadence Allegro PCB SI GXL to make your Multi-GHz Serial Link Work Right out of the Box
December 5, 2007, Donald Telian - Consultant
Webinar: first in a series of webinars for PCB Designers featuring presentations from CDNLive!  More»
Congratulations to the winners of the December 2007
Sourcelink promotion!

   Beceem Communications
Beceem Communications
   Mohammed Ashraf
   Atul Ware
Conexant Systems
   Aditi Sharma
   Dinesh Kumar
Submit your service request on Sourcelink
and be in a draw to win a prize from Cadence!
The more requests you submit, the more chances of your winning!