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Digital IC

Logic Equivalence Checking with Encounter Conformal - Basic & Advanced
December 13, 2007 - December 14, 2007
Cadence Bangalore Office

Verification
Advanced SystemVerilog Language
December 12, 2007 - December 14, 2007
Cadence Bangalore Office

Incisive Comprehensive Coverage (ICC)
December 19, 2007
Cadence Bangalore Office

Silicon Package Board
Allegro PCB SI Foundations
December 17, 2007 - December 19, 2007
Cadence Bangalore Office

We’d like to hear your comments or questions about this newsletter. Email us»


Greetings from Cadence!

Cadence celebrates a landmark achievement - its 100th customer adoption of Encounter Timing System. Already in use by companies such as TSMC, Freescale Semiconductor and Faraday Technology Corp., Encounter Timing System plays an integral role in the design and development of leading-edge chips ranging from networking and telecommunications devices to microprocessors and graphics chips. Read more about it in this issue.

We talked about "What You Design Is What You Get" at CDNLive! India in October. Don’t miss an insightful article in this newsletter by Lead Application Engineer in Custom IC domain, Brajesh Heda, on this topic.

Happy reading.

Rahul Arya
Marketing Director
    Cadence Encounter Digital IC Platform News
Cadence Marks 100th Customer Adoption of Encounter Timing System
Customers Cite Productivity, Predictability and Performance Advantages More»
Routing Based Yield Optimization Preserving Timing
November 6, 2007, Pierre-Olivier Ribet - Cadence Design Systems
Presented at the SAME conference in Sophia Antipolis, France, this methodology is able to apply different kind of optimizations according to the criticality of nets More»
Cadence Announces New RF Technology to Ease Design of Nanometer Wireless Chips
Virtuoso Passive Component Designer Addresses Critical RF Challenges Through Proven Inductor Design, Analysis and Modeling More»
Top
    Cadence Incisive Verification Platform News
Cadence Boosts Engineers’ Productivity with Advances in Enterprise Verification Offering
New Aspect-Oriented Generation Engine and Advanced Transaction-Based Acceleration; Supports Open Verification Methodology for
SystemVerilog  More»
Verification of Low-Power Designs using CPF
October 23, 2007, Noah Bamford - Freescale Semiconductor
CDNLive! 2007 People's Choice Award presentation, illustrates techniques that maximize vertical reuse More»
Micronas Selects Cadence Incisive Plan-to-Closure Methodology for Verification Planning
Cadence and Micronas Conduct Verification Audit to Improve Product Development Process  More»
Top
    Cadence Virtuoso Custom IC Platform News
Designer’s Dream - ’What You Design is What You Get (WYDIWYG)‘
Brajesh Heda, Lead App. Engineer, Cadence Design Systems, India.
In past, manufacturability was able to correlate with designers drawn intent in the form of layout i.e. GDSII shapes (rectangle and squares). There were no limitations to manufacturing equipments  More»
Netlist Based IR Drop and Electromigration Analysis Flow in VirtuosoŽ UltraSim®
Irshad Alam, Custom IC Technical Field Operations, Cadence Design Systems (I) Pvt. Ltd
Introduction
With CMOS process technology scaling down to 65nm and below, IR-drop and electromigration (EM) effects become  More»
Virtuoso Passive Component Designer Now Supports Synthesis for Customer Pcells
November 16, 2007, Bo Wan - Cadence Design Systems
Bo Wan discusses the most important features of Virtuoso Passive Component Designer. More»
Faraday Chooses Cadence VoltageStorm for Advanced 65nm Low-power Signoff
Comprehensive Static and Dynamic Power Analysis Capabilities Enable Accurate Sign-off Analysis for Complex Low-Power Designs More»
Top
    Cadence Allegro SPB Platform News
Cadence Allegro Editor (v15.7) - Allegro Top 30 - Did You Know
November 16, 2007, Vincent Di Lello - Kaleidescape, Inc
This CDNLive! SV2007 People's Choice Award for SPB, provides a collection of (30) time-saving tips, tricks, and obscure functions for Cadence Allegor Editor.  More»
Top
Congratulations to the winners of the November 2007
Sourcelink promotion!

   Arijit Dutta
Freescale Semiconductor
   Beceem Communications
Beceem Communications
   Prasanna Misra
Indian Institute Of Technology
   Sunil Singla
Freescale Semiconductor
   Naveen Kanumuri
STMicroelectronics
Submit your service request on Sourcelink
and be in a draw to win a prize from Cadence!
The more requests you submit, the more chances of your winning!




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