Greetings from Cadence!
This issue has two articles authored by members of the Cadence Custom IC technical field operations team, one by Jagadeesan J on "CMP Aware RC Extraction" and another by Brajesh Heda on "Preparing Data for SubstrateStorm Technology Characterization Tool".
There are several articles authored by our customers and posted on www.cdnusers.org,
some of which are highlighted in this issue. We encourage you to also contribute to the pool of knowledge that is shared on this site. If you would like to contribute an article, simply send it to email@example.com.
| Cadence Encounter Digital IC Platform News|
The Art and Science of Pin Placement for Hierarchical Floorplanning
September 27, 2007, Jack Benzel - Avago Technologies
Winner of the People’s Choice Award in Digital Implementation at CDNLive! Silicon Valley 2007 presents advanced topics in pin placement More»
Interview: Making Reliable Models for SSTA
September 10, 2007, Prashant Maniar - Stratosphere Solutions, Inc.
Prashant Manier believes the current methodology of process characterization at 45 nm is not a good predictor of performance in the presence of variability. This interview explores lower node design methodology. More»
| Cadence Incisive Verification Platform News|
Simplifying Vertical Reuse with Specman Elite
October 5, 2007, Mark Strickland - Cisco Systems
CDNLive! 2007 People's Choice Award presentation, illustrates the advantages of using a CPF-based flow over an ad-hoc solution. More»
Translation of an Existing VMM Testbench into URM
September 27, 2007, Kelly D. Larson - Analog Devices
MVP presentation at CDNLive! 2007, highlights which aspects of the translation were straightforward and which aspects required more attention. More»
Interview: Low-Power Design and Verification using CPF
September 12, 2007, Milind Padhye - Freescale Semiconductor
Milind describes some of the challenges of designing and verifying low-power ICs, as well as how CPF can be used to drive the verification process More»
| Cadence Virtuoso Custom IC Platform News|
CMP Aware RC Extraction
Jagadeesan J, Lead Application engineer, Cadence Design Systems, Inc.
The number of transistors per chip doubles every 18 months, at no cost to customers* and this is achieved through technology scaling, when it progressed to 65nm node and below
Preparing Data for SubstrateStorm Technology Characterization Tool
Brajesh Heda, Cadence Design Systems, Inc.
Understanding doping profiles is essential to characterizing a technology. This application note addresses the following topics in defining doping profiles: More»
Using Thermal Analysis as a Tool to Aid Analog Floorplanning
October 16, 2007, David Schwan - Sirenza Microdevices Inc.
People’s Choice Award for Custom IC at CDNLive! Silicon Valley 2007 shows how Gradient Design Automation’s CircuitFire, a transistor-level analysis tool, operates within the Virtuoso environment More»
Using Spectre RF Noise-Aware PLL Methodology to Predict PLL Behavior Accurately
October 5, 2007, Helene Thibieroz - Cadence Design Systems
People’s Choice Award for Custom IC at CDNLive! Silicon Valley 2007 presents the Spectre RF noise-aware PLL flow More»
| Cadence Allegro SPB Platform News|
Signal Integrity and PCB Layout Considerations for DDR2-800 Mb/s and DDR3 Memory Systems
October 3, 2007, Dr. Syed Bokhari - Fidus Systems, Inc
This CDNLive! SV2007 People's Choice Award for SPB, addresses signal and power integrity requirements of PCBs containing Double Data Rate (DDR) memories. More»