Trainings & Workshops
Digital IC

Voltage Storm Power Rail Analysis
November 5, 2007 - November 7, 2007
Cadence Bangalore Office

CeltIC Nanometer Delay Calculator (NDC)
November 8, 2007
Cadence Bangalore Office

Fire&Ice QXC Gate level Extraction - EXT511
November 13, 2007
Cadence Bangalore Office

Logic Equivalence Checking with Encounter Conformal - Basic & Advanced
November 29, 2007 - November 30, 2007
Cadence Bangalore Office

SOC Encounter
December 10, 2007 - December 12, 2007
Cadence Bangalore Office

Custom IC

Basic Skill Training
October 22, 2007 - October 25, 2007
Cadence Bangalore Office

SKILL Programming for IC Layout Design
October 29, 2007 - October 30, 2007
Cadence Bangalore Office

Virtuoso XL Layout Editor
November 26, 2007 - November 28, 2007
Cadence Bangalore Office

Virtuoso Analog Design Environment
December 3, 2007 - December 6, 2007
Cadence Bangalore Office

Verification

SystemVerilog Language and Application
October 22, 2007 - October 26, 2007
Cadence Bangalore Office

Specman Elite Basic Training
November 5, 2007 - November 7, 2007
Cadence Bangalore Office
Trainer: Prof. Pravin Dakhole

Advanced Specman Training
November 12, 2007 - November 14, 2007
Cadence Bangalore Office
Trainer: Prof. Pravin Dakhole

Incisive Simulator Assertion Based Verification (ABV) Using PSL
November 21, 2007
Cadence Bangalore Office

Incisive Simulation (IUS)
November 29, 2007 - November 30, 2007
Cadence Bangalore Office

Advanced SystemVerilog Language
December 12, 2007 - December 14, 2007
Cadence Bangalore Office

Incisive Comprehensive Coverage (ICC)
December 19, 2007
Cadence Bangalore Office

Silicon Package Board

Allegro PCB SI Foundations
December 17, 2007 - December 19, 2007 Cadence Bangalore Office
  Feedback
We’d like to hear your comments or questions about this newsletter. Email us»


Greetings from Cadence!

CDNLive! India 2007 was a huge success, thanks to your support. In particular, the keynotes by Cadence President & CEO Mike Fister and MindTree Consulting co-founder and COO Suboroto Bagchi were very well received, as was the Tech Talk by IEEE fellow & noted professor Dr Asad Abidi. Click here to read more about the event and see some pictures.

Members of www.cdnusers.org will have access to the CDNLive! India and Silicon Valley presentations shortly, so if you are not yet a member, be sure to sign up today.

Wishing you a Happy Diwali!

Rahul Arya
Marketing Director
    Cadence Encounter Digital IC Platform News
Renesas Technology Adopts Cadence Statistical Timing for 45nm
Cadence Encounter Timing System Leads in Tackling Design Variability  More»
NEC Electronics America Uses Cadence Encounter for High-performance, Low-power ARM11 Processor
Cadence Encounter Synthesis and Implementation Technologies Now One of NEC Electronics America’s Tapeout Methodologies of Choice for ARM Processor Implementations More»
Stratosphere and Cadence Collaborate to Drive 45 Nanometer Design Yield and Performance Higher
Collaboration enables a complete ecosystem for managing impact of process variation on design More»
Top
    Cadence Incisive Verification Platform News
Interview: New SoC Functional Verification Kit Kicks it up a Notch
August 30, 2007, Amjad Qureshi – Cadence Design Systems
hip re–spins are very costly in terms of time and dollars. The new SoC Verification kit can help by enabling re–use, achieving functional closure, and providing automation More»
Metric–Driven Methodology Speeds the Verification of a Complex Network Processor
August 22, 2007, Jean–Paul Lambrechts – Cisco Systems
Discusses Cisco metric–driven process-based approach for the functional verification of their FPGA More»
Customizing and Extending Enterprise Manager Functionality (A Primer)
August 3, 2007, Hamilton Carter – Cadence Design Systems
Shows how the extensibility interface exposes parts of Enterprise Manager’s functionality as an object model so that users can customize the exposed functionality  More»
Top
    Cadence Virtuoso Custom IC Platform News
RFIC Solutions Achieves 2X Increase in Productivity with Cadence Virtuoso Platform
RFIC Solutions, Inc. Successfully Completes 2 Tapeouts Within 1 Month of Adopting Cadence Technology More»
Custom Layout Migration and DFM Optimization using Virtuoso Layout Migrate (VLM)
Vishal Agarwal, Lead Application Engineer, Cadence Design Systems, India Custom Design Challenges: In this competitive world, quality of product and time to market are essential for growth of any semiconductor company. With shrinking technology nodes and increasing circuit More»
Automated Full–Chip Hotspot Detection and Removal Flow for Interconnect Layers of Cell–Based Designs
September 18, 2007, Ed Roseboom – AMD
Describes how fabless designers have integrated this hotspot detection solution in their design flow More»
Top
    Cadence Allegro SPB Platform News
Allegro 16.0 Constraints: Effective Use and 15.x Migration Tips
September 18, 2007, John Schiavone – Cadence Design Systems
Learn how a real–world design is constrained in Allegro 16.0. Customer design was created in Allegro 15.x then constraints re-applied in the v16.0 hierarchical system More»
Top

Congratulations to the winners of the September 2007
Sourcelink promotion!

   Pitchumani Guruswamy
PMC Sierra
   Nikhil Rathod
Qualcomm
   Naman Chaturvedi
National Semiconductor
   Atul Ware
Conexant Systems
   Hiram Prasanna Samuel
Gda Technologies
Submit your service request on Sourcelink
and be in a draw to win a prize from Cadence!
The more requests you submit, the more chances of your winning!




Click