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  Trainings & Workshops
Digital IC

CeltIC Nanometer Delay Calculator (NDC)
September 24, 2007
Cadence Bangalore Office

Logic Equivalence Checking with Encounter Conformal - Basic & Advanced
September 25, 2007 - September 26, 2007
Cadence Bangalore Office

SOC Encounter
October 8, 2007 -
October 10, 2007
Cadence Bangalore Office

Logic Equivalence Checking with Encounter Conformal - Basic & Advanced
October 11, 2007 - October 12, 2007
Cadence Bangalore Office

Voltage Storm Power Rail Analysis
November 5, 2007 - November 7, 2007
Cadence Bangalore Office

CeltIC Nanometer Delay Calculator (NDC)
November 8, 2007
Cadence Bangalore Office

Custom IC

Basic Skill Training
October 22, 2007 - October 25, 2007
Cadence Bangalore Office

SKILL Programming for IC Layout Design
October 29, 2007 - October 30, 2007
Cadence Bangalore Office

Virtuoso XL Layout Editor
November 26, 2007 - November 28, 2007
Cadence Bangalore Office

Virtuoso Analog Design Environment
December 3, 2007 - December 6, 2007
Cadence Bangalore Office

Verification

Incisive Comprehensive Coverage (ICC)
September 19, 2007
Cadence Bangalore Office

Basic SystemVerilog Language
September 26, 2007 - September 28, 2007
Cadence Bangalore Office

SystemVerilog Language and Application
October 22, 2007 - October 26, 2007
Cadence Bangalore Office

Specman Elite Basic Training
November 5, 2007 - November 7, 2007
Cadence Bangalore Office
Trainer: Prof. Pravin Dakhole

Advanced Specman Training
November 12, 2007 - November 14, 2007
Cadence Bangalore Office
Trainer: Prof. Pravin Dakhole

Incisive Simulator Assertion Based Verification (ABV) Using PSL
November 21, 2007
Cadence Bangalore Office

Silicon Package Board

Allegro PCB Editor Advanced Techniques
October 4, 2007 -
October 5, 2007
Cadence Bangalore Office

Allegro PCB SI Foundations
December 17, 2007 - December 19, 2007 Cadence Bangalore Office

  Feedback
We’d like to hear your comments or questions about this newsletter. Email us»


Greetings from Cadence!

CDNLive! India 2007 is scheduled for October 11 at the Leela Palace in Bangalore. Register Now!

This year the event offers over 35 customer sessions, 3 in-depth Tech Talks, a Designer Expo area and more! This is a unique opportunity to network with peers, learn about best practices and the latest technologies, so don't miss it!

Look forward to seeing you at CDNLive! India 2007.

Rahul Arya
Marketing Director
    Cadence Encounter Digital IC Platform News
Interview: Freescale’s Alex Albuerne uses Encounter Timing System to Overcome Timing Challenges
August 3, 2007, Alex Albuerne - Freescale Semiconductor
Alex Albuerne, Freescale Semiconductor, discusses Encounter Timing System in Freescale’s sign-off process. More»
Interview: Logic Designers Get Physical
July 9, 2007, Matt Rardon - Cadence Design Systems
Matt Rardon discusses physical predictability and how the Cadence Logic Design Team Solution closes the gap between logical and physical views of a design. More»
Top
    Cadence Incisive Verification Platform News
New Kit from Cadence Cuts Risk and Time for Adopting Functional Verification Methodology
Integrates Proven Methodology, IP, and Applicability Consulting to Address Design and Verification Challenges in Wireless and Consumer Markets. More»
Cadence and Mentor Graphics Deliver Interoperability with Open SystemVerilog Verification Methodology
The Open Verification Methodology Enables Simulator, Verification IP, and Language Interoperability to Deliver on Promise of SystemVerilog More»
Customizing and Extending Enterprise Manager Functionality (A Primer)
August 3, 2007, Hamilton Carter - Cadence Design Systems
Shows how the extensibility interface exposes parts of Enterprise Manager’s functionality as an object model so that users can customize the exposed functionality.  More»
Top
    Cadence Virtuoso Custom IC Platform News
Substrate Coupling Analysis in Integrated Circuits
Brajesh Heda, Lead Engineer, Cadence Design Systems, India.
In recent times, mixed signal and RF circuit designers are constantly trying to integrate low-noise and sensitive analog More»
Utility for Extracting and Highlighting Net Connectivity in Virtuoso
August 6, 2007, Derek May - Micron Technology
Describes the extensive benefits of having a custom, skill-based, net extraction utility. More»
Cadence Extends DFM Solution with Acquisition of Design-side Litho and Variability Leader Clear Shape Technologies
Addition of Clear Shape Helps Cadence Bring Advanced Physical and Electrical DFM Modeling to Design Engineers More»
Top
    Cadence Allegro SPB Platform News
Faraday Adopts Cadence Connectivity-Driven SiP Co-Design Capabilities
Cadence SiP Digital Layout for Constraint- and Rules-Driven IC Package Design Strengthens Faraday’s Substrate Design Capability and Streamlines Integrated Flow More»
Interview: SiP16.0 extends RFSiP Implementation to Parasitics/Simulation
July 18, 2007, Taranjit Kukal - Cadence Design Systems
SiP16.0 release extends the RFSiP Implementation flow offered in 15.7 to Parasitics/Simulation flow. This cdnusers interview briefly discusses the most important features. More»
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