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  Trainings & Workshops
Digital IC

SOC Encounter
August 29, 2007 –
August 31, 2007
Cadence Bangalore Office

Voltage Storm Power Rail Analysis
September 12, 2007 – September 14, 2007
Cadence Bangalore Office

CeltIC Nanometer Delay Calculator (NDC)
September 24, 2007
Cadence Bangalore Office

Logic Equivalence Checking with Encounter Conformal – Basic & Advanced
September 25, 2007 – September 26, 2007
Cadence Bangalore Office

SOC Encounter
October 8, 2007 – October 10, 2007
Cadence Bangalore Office

Logic Equivalence Checking with Encounter Conformal – Basic & Advanced
October 11, 2007 – October 12, 2007
Cadence Bangalore Office

Custom IC

Virtuoso AMS Designer
September 6, 2007 – September 7, 2007
Cadence Bangalore Office

Virtuoso UltraSim Full–Chip Simulator
September 10, 2007 – September 11, 2007
Cadence Bangalore Office

Basic Skill Training
October 22, 2007 – October 25, 2007
Cadence Bangalore Office

SKILL Programming for IC Layout Design
October 29, 2007 – October 30, 2007
Cadence Bangalore Office

Virtuoso XL Layout Editor
November 26, 2007 – November 28, 2007
Cadence Bangalore Office

Verification

Incisive Simulation (IUS)
August 23, 2007 –
August 24, 2007
Cadence Bangalore Office

Incisive Simulator Assertion Based Verification (ABV)
Using PSL
August 30, 2007
Cadence Bangalore Office

Specman Elite Basic Training
September 10, 2007 – September 12, 2007
Cadence Bangalore Office
Trainer: Prof. Pravin Dakhole

Incisive Comprehensive Coverage (ICC)
September 19, 2007
Cadence Bangalore Office

Basic SystemVerilog Language
September 26, 2007 – September 28, 2007
Cadence Bangalore Office

SystemVerilog Language and Application
October 22, 2007 – October 26, 2007
Cadence Bangalore Office

Silicon Package Board

Allegro PCB Editor SKILL Programming Language
August 13, 2007 –
August 14, 2007
Cadence Bangalore Office

Allegro PCB Editor Advanced Techniques
October 4, 2007 – October 5, 2007
Cadence Bangalore Office

Allegro PCB SI Foundations
December 17, 2007 – December 19, 2007 Cadence Bangalore Office

  Feedback
We’d like to hear your comments or questions about this newsletter. Email us»


Greetings from Cadence!

We are excited to announce that CDNLive! is scheduled for October 11 & 12 at the Leela Palace, Bangalore. Please mark your calendars. A separate notice regarding registrations will be sent out in a few weeks. This year's event promises more sessions, international speakers, and an exhibition area. Don't miss it!

We would also like to highlight an article posted on cdnusers.org by our customer Tata Elxsi on "Developing a Gigabit Ethernet VIP Using the Plan to Closure Methodology Featuring SystemVerilog". Cdnusers.org is a great platform to discuss the latest design trends and share your knowledge with an international audience. Submit your contributions now!

Also in this edition - read about how Palladium has helped Winbond speed functional verification of complex graphics IC designs by 5,000 times over simulation alone by integrating the environments for hardware, software, and firmware.

Rahul Arya
Marketing Director
    Cadence Encounter Digital IC Platform News
Cadence Extends Integrated SiP Technologies Into the Latest Custom And Digital Design Flows
Cadence Leads the SiP Industry by Delivering Significant New Design Capabilities and Productivity Enhancements to System-Level IC and Package Co-Design More»
Debugging Clock Trees Will Now Be Easier
Martin Spohr, NEC
Frank Guffler, NEC

In the RTL world, clocks are ideal signals with few difficulties. More»
Improving Productivity Using Formal Analysis by Designers
June 15, 2007, Eric Faehn - STMicroelectronics

This Best Paper Award in the Digital area at CDnLive EMEA discusses several important aspects of deploying formal analysis in recent projects at STMicroelectronics More»
Top
    Cadence Incisive Verification Platform News
Winbond Israel Chooses Cadence Incisive Palladium Series to Ease Design Verification
Integrated Environment for Hardware, Software, and Firmware Speeds Functional Verification of Complex Graphics IC Designs by 5,000 Times over Simulation Alone More»
Siemens IT Solutions and Services Adopts Cadence’s Assertion-based VIP to Speed Development
Assertion–Based VIP with Incisive Formal Verifier Improves Quality, Ensures Protocol Compliance and Cuts Weeks from Schedule More»
Developing a Gigabit Ethernet VIP Using the Plan to Closure Methodology Featuring SystemVerilog
Sarvana Kumar, TATA ELXSI Limited
Jagvinder Yadav, TATA ELXSI Limited
Gaurav Singh, TATA ELXSI Limited

Discusses verification reuse methodology for developing a complex protocol such as a Gigabit Ethernet.  More»
Top
    Cadence Virtuoso Custom IC Platform News
Cadence and SMIC Collaboration Validates RF Design Kit for Wireless
IC Design
Companies Will Jointly Host RF Workshops in China More»

Jazz Semiconductor Teams with Cadence on Support for Cadence RF and AMS Design Kits
Cadence Design Kits Enable Jazz Customers to Streamline Design Cycles and Achieve Design Success More Rapidly More»

Toumaz Technology Achieves First Silicon Success with Cadence Virtuoso Multi–Mode Simulation
Cadence Virtuoso AMS Designer Simulator Helps Toumaz to Accelerate Tapeout of Its SensiumTM Ultra Low Power Sensor Interface and Transceiver Platform More»
Top
    Cadence Allegro SPB Platform News
What’s New in Cadence Allegro 16.0
Discover how the Cadence® Allegro® platform improves design efficiency and designer productivity by dramatically shortening the learning curve in the adoption of new solutions and enhancing ease–of–use. More»
Effective Modeling and Analysis of EMI Effects on Printed Circuit Boards
Kun Zhang, Huawei Technologies Co, ltd.
Zhen Mu, Cadence Design Systems

With the increasing of signal frequencies in high speed systems, it is critical for electronic products to pass EMI test before going into the market. More»
SigXplorer Batch Mode Simulations
Lance Wang, Cadence Design Systems

SigXplorer is a topology exploration tool that allows users to explore solution spaces and simulate advanced buses. More»
Top

Congratulations to the winners of the July 2007
Sourcelink promotion!

Arm Holdings
Gda Technologies
Intel
Conexant Systems
Wipro
Submit your service request on Sourcelink
and be in a draw to win a prize from Cadence!
The more requests you submit, the more chances of your winning!