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Home > Cadence India > Technology on Tour 2013

Technology on Tour 2013 

May 15, 2013 – Bangalore  
May 17, 2013 – Hyderabad  
May 21, 2013 – Pune

Join Cadence at one of our Technology on Tour sessions to learn about the latest solutions addressing the design and verification needs of the global electronics industry. Our experts will share with you the newest products, flows, and methodologies to help you develop advanced silicon, systems-on-chip (SoCs), and systems – faster and more profitably.

May 15, 2013 – Technology on Tour Seminar, Bangalore
Park Plaza Bengaluru
Marathahalli, Outer Ring Road,
Bangalore 560037

May 17, 2013 – Technology on Tour, Hyderbad
Taj Deccan
Road No 1, Banjara Hills

May 21, 2013 – Technology on Tour Seminar, Pune
Four Points By Sheraton
5th Mile Stone, Nagar Road

What you will learn

Verification Track
In this track, you will learn the latest and greatest in advanced verification technologies/methodologies across areas including simulation, formal verification, and low-power verification, which will help you in closing your quality verification faster. You will also hear about the latest in verification IP (VIP), design IP, and memory models, which can cut verification and design time and speed time to market.

Digital Track
In this track, we will share how Cadence is transforming digital design with the new Encounter® RTL-to-GDSII flow. You will also learn how you can achieve better power, performance, and area (PPA) for your designs while shortening design cycle times using our design methodology. We will cover some of the latest design methodologies in this seminar: high performance, giga-scale, advanced node, low power, and mixed signal.

The Hyderabad Technology on Tour will include some front-end design sessions.

Custom IC Track
In this track, you will learn how Cadence® custom IC solutions automate many of the routine tasks involved in custom IC design, allowing engineers to focus on differentiating their designs. Topics covered include the recently launched Virtuoso® Advanced Node technology, the latest updates on Virtuoso 6.1X, and Cadence Virtuoso Foundation IP Characterization technology.

Mixed-Signal Track
Come to this session to learn how the Cadence Mixed-Signal Solution addresses verification and implementation challenges and delivers a comprehensive, interoperable, and production-proven methodology in which all design steps—early design planning, front-end design, functional verification, physical implementation, signoff, and packaging—are shared responsibilities between analog and digital teams.

Front End Digital Design Track
In this track you will learn about the latest advancements in front-end digital technologies and methodologies centered around RTL-based physical synthesis, test, low power, and formal verification in relation to engineering change order (ECO) automation. Learn from R&D’s latest developments, and find out how you can leverage these capabilities immediately to help accelerate design schedules while maximizing design quality. You will also learn how to quickly enhance your team's expertise of key methodologies with readily available, self-packaged Rapid Adoption Kits (RAKs).

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