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Cadence Design Contest 2013 

Announcing the launch of the Cadence Design Contest 2013!

Deadline to Submit: Friday, 12th April 2013

Categories
There will be two categories for which prizes will be given. A winner will be chosen in both these categories:
1. Full time B.E / B.Tech students
2. Full time M.E. / M.Tech students

Design requirements
Submissions for both categories should be in either Analog, Digital or Board Design and can be in either of the following 2 design areas:
  • Operational chip design - designs have been implemented and tested
  • Conceptual design - need not have been implemented but must have been thoroughly simulated and must include a test plan
Evaluation Criteria
Submissions are judged by an Expert Committee comprising of representatives from the industry and Cadence experts on pre-defined criteria including:
  • Inventiveness
  • Complexity and feasibility of project
  • Breadth of Design
  • Effective Use of Cadence technologies
  • Presentation and clarity of communication
Timeline
Call for papers open 11th Feb 2013
Call for papers closed 12th April 2013
Submitters informed - 1st round 31st May 2013
Papers due from submitters - 2nd round 5th July 2013
Submitters informed - 2nd round 12th Aug 2013
Top teams final live presentation 1st Week of Sept ‘13
Winner announced 2nd Week of Sept ‘13

How to submit
  • Click on the “Submit Now” link at the end of this page to go to the Registration Form.
  • Fill in the Registration Form. Once you click “Submit” at the end of the page you will get a link to download the Abstract Submission Form.
  • Download and save the Form.
  • All mandatory fields of the Abstract Submission Form must be filled in full. Incomplete forms will not be accepted.
  • Please email your Abstract Submission Form in Word format ONLY (no PDFs) to Cadence Design Contest India (designcontest_india@cadence.com)
  • Abstract must be a maximum of 350 words – around 1 ½ pages.
Contest Rules
  • The University / Institute must be enrolled as part of the Cadence University Program at the time of submitting the abstract for the Contest.
  • Maximum of 4 students per submission.
  • The design work submission must have taken place as part of the students' course or research work at the university / institute, and must have been completed within 12 months prior to the submission deadline.
  • All designs must use predominantly Cadence technology.
  • Diagrams are allowed.
  • Abstract must provide high level specs / framework with measurable parameters that demonstrate the project's uniqueness, such as:
    • The intended product / application (specify domains where this will be valuable)
    • Enhanced low power consumption (capability to run off battery power for longer)
    • Increased performance (increase of throughput and time saving achieved)
    • Newer functionality introduced
    • Verifications frameworks used
  • Abstract must clearly describe how Cadence tools helped in the design analysis, decisions and debugging.
  • Abstract must quantify the completeness of the implementation vs original specifications of the project/design work. Gaps in implementation must be identified and their impact to the original intent of the project / design work must be evaluated.
Some project titles from previous Cadence Design Contests:
  • Bachelor's category:
    • Design and Implementation of Low Power Pipelined FFT Processors Using Self Timed Adders
    • Implementation of a Low Power, Area Efficient Health Analyzer, HealthComm
    • Design Of Ultra Low Power, Low Noise Implantable Neural Recording Amplifier For Brain Machine Interface
  • Master's category:
    • Low Power, Low Noise Signal Conditioning Chip with Differential “Resistance to Frequency” Converter for Resistive Bridge Sensors
    • A 2.4 GHz Ultra Low Power, Ultra Low Voltage Low Noise Amplifier Design Improving the Load Transient Response of an Output Capacitor-less Low Drop-out Regulator for the SoC Applications


For more information please contact designcontest_india@cadence.com

 
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