Global synthesis that enables concurrent optimization of timing, area, and power Encounter RTL Compiler allows engineers to look across the entire design as they employ concurrent optimization techniques, such as making tradeoffs among timing, area, and power.
To maximize performance, decrease die size, reduce power consumption, and boost productivity, designers need a global synthesis solution that enables concurrent optimization of timing, area, and power. Encounter RTL Compiler, a key component of the Cadence Logic Design Team Solution, delivers production-proven global synthesis for faster, smaller, and low-power chips in less time. With its unique set of patented global-focus algorithms, combined with new physically-aware optimization and analysis, Encounter RTL Compiler cuts design time while ensuring the highest quality of silicon.
Features/Benefits
- A well-balanced logic structure isolates critical paths and reduces power, area, and congestion in off-critical logic
- Enables faster timing closure through place-and-route
- Physical layout estimation eliminates the need for wireload models
- Integration with First Encounter Silicon Virtual Prototyping provides real physical timing to logic optimization and analysis
- Lowers power consumption through single-pass multi-Vt optimization, hierarchical and multi-stage clock gating, MSV support, power shutoff, and state-retention power gating
- Shrinks die sizes with multi-objective optimization
- Speeds up time to design closure with multi-mode synthesis optimization and analysis
- Superior capacity increases productivity by enabling chip-level synthesis and eliminating manual partitioning, budgeting, and reassembly
- Uses standard inputs and outputs to ease adoption
Logic Synthesis Survey
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Click here to get to the survey » The closing date for completing the survey is 21st November 2008
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