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Vertical Solution for PCI Express PCI Express is positioned to become the dominant high-speed serial communication interface within the next 1-2 years. Whether your application is graphics, multimedia or communications, and your platform is mobile, desktop or server, Cadence has PCI Express solutions to meet your needs. This includes the engineering services, design software and IP required to deliver integrated IC and system development. Migrating from legacy PCI to PCI Express creates new challenges for IC and system developers. In the past when integrating new technology you could rely on point solutions from multiple suppliers. However, high-speed serial interconnects present additional challenges in leading-edge digital and analog design and verification. For successful product development in today's fast-moving markets, you need an integrated solution that supports every stage of the IC and PCB development process. The Cadence Vertical Solution for PCI Express contains the following major components:
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Implementation IP: PEX (1 to 8 lane) and PHEX (16 lane) Endpoint Controllers and RaSer PHY cores for PCI Express from Rambus | |
Verification IP: Cadence PCI Express eVC and acceleratable VIP as well as PureSpec VIP from Denali | |
SpeedBridge rate-adapter card, for in-circuit emulation with Palladium® | |
Silicon Design-in Kits, to accelerate silicon-package-board design and analysis using the Cadence Allegro® system interconnect design platform | |
Protocol Analysis tools from Catalyst | |
Engineering Services to assist with IC/board-level design, integration, and verification
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| Vertical Solution for PCI Express Architecture |
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Engineering Services
Working as your design partner, Cadence brings a lengthy track record of successful experience helping customers integrate PCI Express into their ICs, SOCs and systems.
Implementation IP
Press Release
- The Cadence PEX Endpoint Controller IP integrated with Rambus' PCI Express PHY IP, has passed PCI-SIG compliance testing and been added to the PCI-SIG Integrators List.
Soft IP for PCI Express
Cadence's Endpoint Controller cores for PCI Express provide the best solutions available today for both flexibility and high performance. PEX supports 1 through 8 lane applications and provides the choice of a generic transaction layer for ease of use or a lower transaction layer enabling developers to tailor the transaction layer on their product. It has been architected to be suitable for mapping to FPGA and has a wide range of configuration options to enable customers to select extended capabilities as required, for example, or to leave these out and save gates.
PHEX is a 16 lane solution which is suitable for high bandwidth applications such as graphics. It provides a 16 lane link with auto negotiation through x8, 4, 2 and 1 lanes.
Rambus RaSer PHY cores for PCI Express
Rambus' PHY cores for PCI Express are the most robust solutions available in the market today. Available for 180nm, 130nm and 90nm processes on leading foundries, the Rambus PHY cells are based on a proven architecture and tested in silicon, and at the same time have been optimized for minimum power and footprint. Rambus are world class experts in the delivery of serial link and signal integrity support. Rambus products can be delivered as Off The Shelf (OTS) solutions or tailored to meet your exact requirements using Cadence design services.
Cadence and Rambus IP cores for PCI Express have been successfully tested at the PCI-SIG; Compliance Workshops both individually and combined - further reducing risk for developers.
The Endpoint Controller and PHY cores were developed using the Cadence Encounter® digital IC design platform and the Cadence Incisive® functional verification platform, for unmatched implementation speed, design-flexibility, and quality of silicon. Although these cores can be implemented and verified effectively within design flows containing tools from other EDA vendors, the full-complement of scripts and configuration-files delivered with these cores aids developers in saving significant time and effort when using Cadence-based Flows.
Verification IP (VIP)
Cadence offers world class VIP solutions for PCI Express - including our PCI Express e Verification Component (eVCs), our acceleratable IUS VIP core and PureSpec VIP from Denali. These provide Cadence customers with unmatched flexibility in their choice of verification methodology.
eVCs offer ease of use within a highly powerful verification environment. They integrate automatic stimulus generation, assertion checking and functional coverage analysis all within a single configurable, extensible VIP. eVCs automatically generate every transaction type for all three PCI Express layers and each layer can be selectively enabled or disabled as required. They are fully reusable at the module, chip, and system levels greatly reducing verification environment bring-up time and improving end-product quality.
Cadence IUS VIP cores provide acceleratable PCI Express VIP for customers that need to verify massive transaction volumes.
For customers that prefer C-based verification IP Denali's PureSpec is a complete solution for verifying compliance and compatibility of PCIe designs. PureSpec-PCIe is architected to ensure high-quality, high-performance, and seamless integrations.
Cadence's verification IP solutions are further enhanced through the availability of Services that enable developers to optimize their verification methodology.
SpeedBridge for PCI Express
The Cadence SpeedBridge for PCI Express enables customers to test PCI Express systems under real traffic conditions using the Cadence Palladium hardware emulator. The SpeedBridge manages communications between the developer's software development platform (running on a PC) and the emulator.
By synthesizing the design under verification to the Palladium developers are you able to achieve verification speed up of 1,000 to 10,000 times. Enabling hardware/software co-design can cut full product development schedules by up to 50%.
Silicon Design-in Kits
Cadence Silicon Design-in Kits operate within the Allegro system interconnect design platform, aiding PCB designers in developing optimal constraints to drive PCB floorplanning, routing and the verification process; and making direct use of silicon and behavioral models earlier in the design cycle.
The Silicon Design-in Kit for PCI Express includes:
| Tutorial videos and reference boards to help you get up to speed quickly | | Reference schematics and PCB layouts with embedded constraints | | Proven simulation models and stimulus that enable customers to begin viewing waveforms within minutes |
By using these kits, silicon companies can shorten time-to-socket and ultimately time-to-volume production by shortening systems companies' time to design-in their chips. Protocol Analysis Tools: Bus Analysers/Exercisers
Catalyst develop bus-specific development systems, commonly known as "Bus Analyzers" which capture traffic across the bus for post-processing and analysis and inject traffic onto the bus to stimulate a Unit Under Test (UUT).
During debug Catalyst Analysers and Exercisers for PCI Express greatly accelerate bringing up and analysis of the unit under test. Cadence Engineering Services teams have used Catalyst bus analysers and exercisers on IP and customer IC projects and have found them to be extremely useful tools, particularly in preparing for PCISIG Compliance Workshops.
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