Home > A Cadence Vision: EDA360

EDA360 Video Highlights

EDA360: RT @SteveLeibson A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle http://t.co/lMRwaynR #EDA360 — About 22 days ago
EDA360: A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle http://t.co/Bs6kyC4K — About 22 days ago
EDA360: RT @SteveLeibson Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exp... http://t.co/6qVzoOco #EDA360 — About 26 days ago
See more tweets »

Cadence Extends Verification IP Catalog -EETimes - 28 Feb 2011
Cadence Takes Another EDA360 Step -Gabe on EDA - 28 Feb 2011
Cadence Drives Giga-gate/Gigahertz Design at 28nm with New Digital End-to-end Flow - 31 Jan 2011
Cadence Exec: EDA Needs 'Breakaway Value' - EE Times - 2 Feb 2011
Spreadtrum tapes out 40-nm LP chip using Cadence Silicon Realization - EE Times - 21 Jan 2011
Warren Savage On: The Geometry of EDA 360 - Electronics Weekly - 17 Jan 2011
The Future Of Electronic Design Automation - PC Today - 12 Oct 2010
A Few Rounds on EDA360 - IC Design & Verification Journal - 23 Nov 2010
EDA 'co-opertition'—a new era or more lip service? - EE Times - 11 Nov 2010
John Bruggeman of Cadence on EDA360 at ARM Techcon 2010 - ARMDevices.net - 11 Nov 2010
A New Vision For the EDA Industry - New Electronics - 3 Nov 2010
Cadence Advocates Application-Driven Design - Donovan's Brain - 2 Nov 2010
Who Does What - Low-Power Engineering Community - 29 Oct 2010
More news »

EDA360 Overview

The semiconductor and system design industry is undergoing a disruptive transformation so profound that even the best-known companies will be affected. This transformation is not about new electronic design automation (EDA) tools. It’s not about new methodologies. It’s not about the functional verification crisis or the move to electronic system-level design. It is about something much larger.

The EDA industry now stands at a crossroads where it must change to continue as a successful business. The change begins with a shift from traditional design creation to integration in the electronic systems industry, and it results in a new focus on profitability.

Change begins with EDA360, a new vision for what the EDA industry can become.

Moving from Design Creation to Integration
A few large semiconductor companies will continue to follow Moore’s Law and migrate to lower process nodes that offer power, performance, and die-size advantages. These companies are traditional design creators. And while they provide a crucial role, only a few can exist.

Some of these design creators will redefine themselves to become integrators. They will integrate at the silicon, SoC, and system levels. As such, they need the most effective means of locating, evaluating, and sourcing IP. They will rely on externally designed silicon and bare-metal software IP, they will tend to stay at mature process nodes. They will need to verify and test mixed-signal platforms and SoCs, and they will invest heavily in embedded software development. These integrators will become application-focused platform providers, not just chip providers.

So far the EDA industry has only served the needs of traditional creators, who are focused on productivity. Integrators, however, are focused on profitability. And to close the profitability gap without sacrificing quality or schedule, integrators require a different set of tools and capabilities.

Realizing the Way Forward for EDA
EDA360 provides an expanded, 360-degree vision of a revitalized EDA industry that serves integrators as well as creators. EDA360 will close the profitability gap through integration-ready IP creation, integration, and optimization. Given that embedded software can take up half the cost of SoC development, EDA360 also supports hardware/software integration and verification. While traditional EDA focuses on engineering teams only, EDA360 will provide capabilities for project and business management.

With EDA360, we start with an understanding of the software applications that will run on a given hardware/software platform, define system requirements, and then work our way down to hardware/software IP creation and integration.

EDA360 supports three fundamental capabilities: EDA360 will ensure a vibrant, pioneering electronics industry, one that will not only change the way we work and play, but also provide solutions for energy conservation, the environment, healthcare, education, and transportation. By collaborating with our ecosystem partners, we can provide the necessary support for System, SoC, and Silicon Realization and enable a new era of application-driven design.

System Realization

  Just Launched!
New Cadence System Development Suite delivers four integrated platforms for concurrent hardware/software design and verification.
Watch video »
  System Realization at NVIDIA
Leading GPU supplier uses Cadence System Development Suite for fast HW/SW integration and high-quality product creation.
Watch video »
Applications are Driving System Requirements
Electronics products today are all about the “apps.” Industry newcomers who focus their differentiation on game-changing software applications are challenging even the most established companies to stay commercially viable and develop systems that support the latest apps.

But the traditional approach to system development is disjointed. Applications, software, and hardware are developed by geographically dispersed teams using different tools and IP. The usual steps are to build the hardware, append software later, and let someone else worry about the applications running on pre-built hardware.

The Hardware-First Paradigm is No Longer Feasible
EDA360 uses an application-driven approach to System Realization. Developers start by envisioning the application; they can then design at the system level, work down to the software, and finally build or buy the hardware.

A “realized” system comprises a hardware/software platform with one or more SoCs plus an embedded software infrastructure that typically includes an operating system (OS), middleware, and reference applications. The system must comprehend all levels of the software stack, from the bare-metal software and OS to the libraries and applications.

More and more industry newcomers are outsourcing hardware design. They are also increasingly dependant on semiconductor providers to supply portions of the software stack. What they are demanding, in effect, are application-ready platforms with hardware and software for specific apps. Delivering these platforms is now as vital as producing the most power-efficient silicon.

EDA Must Support a New Set of Capabilities
The application-driven approach places new demands on system integrators and EDA providers. No single vendor can provide all the solutions needed for hardware/software creation, integration, and verification. That is especially true for System Realization, where both embedded software and hardware expertise are required.

EDA360 advocates ecosystem collaboration (among embedded software companies, IP providers, and customers) along with open standards to provide five key capabilities:
  • Early software development
  • Application-specific system integration
  • Application-specific system verification
  • Driver development kits
  • Application development kits
EDA360 also offers metric-driven verification capabilities to help companies manage application-driven System Realization projects at the enterprise level. Using a metrics-driven approach, design and verification managers can create an executable verification plan that identifies key project metrics, executes simulation engines, and tracks coverage. They can then review reports and better determine progress toward verification closure. With such metrics, system integrators and EDA companies can allocate verification resources more effectively and focus on closing the profitability gap.

SoC Realization

  Driving SoC Realization
The open integration platform provides a comprehensive set of capabilities to develop today’s complex SoCs efficiently and profitably. Read more »
  What SoC Realization Is And How to Enable It
The open integration platform, along with integration-optimized IP, will enable successful SoC hardware and software development.
View the video »

A Software-Defined Approach
While System Realization produces a complete hardware/software platform ready for applications deployment, SoC Realization ensures the successful development of a single system on chip (SoC) to meet system needs. Traditionally, SoCs are considered “done” once the silicon is completed. But with EDA360, SoC Realization is not complete without software device drivers for each hardware subsystem.

Driver software allows the operating system (OS) and the applications to take advantage full of specialized hardware features. EDA360 advocates that these drivers be developed with the SoC rather than tacked on later—and that leads to a new view of how silicon intellectual property (IP) should be provided.

An Expanded Definition of SoCs: the IP Stack
From a silicon standpoint, your basic SoC is a configurable IC with a processor, some custom logic, and a memory controller. EDA360 calls for an expanded definition of SoCs that includes the “bare-metal software” along with a more comprehensive view of IP as a “stack”—from the physical and protocol layers to the software device drivers along with associated verification IP and design constraints.

Typically, hardware is built first and drivers are written later, usually by someone unaware of the differentiating capabilities of the hardware. This leaves two options: develop a custom driver, which is expensive, or purchase a generic driver, which won’t leverage all of the hardware capabilities. In either case, the applications are disconnected from the underlying hardware system. EDA360 repairs this weak link by bundling device drivers with silicon IP.

Constraint-Driven, Integration-Ready IP
SoC Realization is most efficient when multiple IP stacks are assembled into IP subsystems, which support major hardware subsystems. EDA360 calls for a constraint-driven approach to ensuring integration-ready IP. To optimize IP for integration, design constraints are needed for all parts of the IP stack—including analog hard macros, synthesizable digital IP, and driver software. A thorough understanding of power, timing, and area constraints makes the integration of IP into an SoC quicker, easier, and less risky. Without such constraints, bugs creep into the interfaces between IP subsystems, comprising overall system functionality and increasing verification costs.

An open integration platform
Developing integration-ready IP for SoC Realization requires making it easier for IP creators to build drivers and facilitating metric-driven IP verification to eliminate the need for re-verification of IP. SoC integrators need a framework for this—and so EDA360 calls for an open integration platform.

The platform runs what-if analysis to determine the best possible architecture and integration. It develops an initial SoC architecture and then quickly integrates verified IP into verified SoCs. It is driven by an Integration Design Environment (analogous to the IDE or Integrated Development Environment used by software developers). And it is based on open standards like the OpenAccess database, the Open Verification Methodology (OVM), the IP-XACT format for IP descriptions, and the SystemC® TLM 2.0 modeling standard. The open integration platform leverages existing capabilities: metric-driven verification, low-power design, mixed-signal implementation and verification, and hardware/software integration.

Integration-ready IP thus requires a collaborative ecosystem. EDA companies, embedded software and OS vendors, IP providers, foundries, and end-user companies must all work together to expand the definition of IP to bare-metal software and complete subsystems.

Silicon Realization

  How Cadence Tackles Challenges in Silicon Realization
Holistic solutions with fundamental new architectures: design intent, design abstraction and design convergence.
View the video »

  Silicon Realization Enables Next-Generation IC Design
Unified design intent and verification, higher-level design abstraction, and a top-down, bottom-up methodology for faster design convergence.
Download the white paper »

Deterministic Path to Silicon Success
Silicon Realization has been the predominant focus of the EDA industry since its inception. But as the global electronics industry moves toward application-driven System Realization, the scope and complexity of getting a design into silicon is mushrooming.

Silicon Realization goes far beyond the traditional view of “mixed-signal” design, which typically involves the importation of hard analog macros into a digital SoC. It also involves the creation of full-custom digital, analog, and RF IP blocks and ICs. And it means integrating blocks (that were entire chips in previous process generations) into SoCs that support broad ranges of functionality.

While System Realization and SoC Realization are primarily tasks for integrators who concentrate on profitability, both design creators and integrators perform Silicon Realization, and they focus on productivity. The fundamental challenge: being able to concurrently tackle functional, electrical, and physical requirements and it use of intent, abstraction, and convergence.

Close the Productivity and Profitability Gaps
To address the needs of both design creators and integrators, EDA360 supports a number of approaches to close the productivity and profitability gaps in Silicon Realization.
  • Design convergence. The emerging application-driven approach starts with the application, defines the system, and then abstracts the hardware and software requirements from the system definition. But it’s not all top down. Information must flow upward from the silicon level as well. It’s critical to understand power, performance, and cost at the system level, and this can happen only if there is convergence. Convergence is the ability to run early-stage ‘what if’ analyses of power, performance, cost, and packaging with meaningful data. Convergence also speeds design closure, eliminates iterations, makes engineering change orders (ECOs) less disruptive, and reduces the risk of re-spins.
  • Raise the level of abstraction. The major trend in digital design and verification is transaction-level modeling (TLM). Analog designers are using behavioral modeling languages such as Verilog-AMS, and can now simulate analog circuits in a digital environment using the “wreal” data type. However it’s done, higher levels of abstraction enable greater automation of subsequent design activity, streamline the design process and, by eliminating unnecessary steps, reduce costs.
  • Apply unified design intent. A single and complete representation of design intent eliminates errors and unnecessary iterations throughout the Silicon Realization flow. Working from a common set of design constraints allows a global knowledge transfer among design teams, reduces the risk of specification misses and re-spins, and it ensures that late-stage changes are tracked and implemented correctly and consistently throughout the design process.
  • Consider software as a service. EDA360 is not just about tools and technology; it also expands into business and engagement models. Whether it’s lack of expertise or subtle differences in infrastructure, many design teams struggle to deploy an environment even when using a reference flow defined by a production partner. Using Software as a Service (SaaS) allows a design environment to be fully configured and externally hosted using either dedicated third-party servers or “cloud” computing. SaaS helps designers leverage the capabilities they need, when they need it, which boosts productivity and accelerates profitability.

Contact Cadence

  * Required fields
First Name *
Last Name *
Company *
Email *
Country *
Technology Interest *

Comments *
Contact Preference *