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Cadence Theater
At the Cadence® Theater at DAC, Cadence customers and partners highlighted their successes using Cadence products and technologies. Session recordings are available below.

Monday, June 03, 2013
6/3/2013 9:00:00 AM
Session Time Company Topic
View Presentation 09:00 AM Marvell Practical ECOs using Conformal ECO
Watch presentation 10:00 AM X-Fab Rapid Adoption of Advanced Cadence Design Flows Using X-FAB's AMS Reference Kit
Watch presentation 11:00 AM Freescale Best Practices in Verification Planning
Watch presentation 12:00 PM Contemporary Verification Consultants Objective Measure of Verification Quality with IEEE 1647 (e) and Incisive HAL
Watch presentation 12:30 PM AMD Complementing In-Circuit Emulation with Virtualization for Improved Efficiency, Debug Productivity and Performance
Watch presentation 02:00 PM ARM Accelerating Time to Market with ARM Software Development Tools and the Cadence System Development Suite
Watch presentation 02:30 PM Broadcom Faster System Bring-up with an Embedded Testbench on Palladium
Watch presentation 03:00 PM PMC Implementing Power Gating Flow with CPF
Watch presentation 04:30 PM Mobile Semiconductor Statistical Characterization Approach Using Liberate MX with 40nm Low Voltage SRAM
Watch presentation 05:00 PM GLOBALFOUNDRIES Innovating Together to Build Exceptional PDKs
Watch presentation 05:30 PM ARM ARM Cortex®-A15 Hard Macro and Artisan® POP™ Proof Points

Tuesday, June 04, 2013
6/4/2013 9:00:00 AM
Session Time Company Topic
Watch presentation 09:30 AM TowerJazz Substrate Noise Isolation Extraction/Model Based on Foundry Measurement Using Cadence Analog Flow
Watch presentation 10:30 AM Silicon Labs Power Mode Verification in Mixed-Signal Chips
Watch presentation 11:00 AM Texas Instruments Highly Scalable Multicore ARM A15 Verification with Specman/e.
Watch presentation 11:30 AM Forte and Cadence How to Broadly Deploy SystemC High-level Synthesis for Production Hardware Design
Watch presentation 12:30 PM Marvell SoC Interconnect Analysis for Effective Verification, Architectural Exploration and Post-silicon Debug
Watch presentation 01:30 PM ST Microelectronics IPVS and PVS BCD deck support
Watch presentation 02:00 PM Methods2Business Towards Formally Proven Embedded System Design with an Unambiguous HW/SW Contract
Watch presentation 02:30 PM Tensilica/Cadence Customizable Processor Basics
Watch presentation 03:00 PM Freescale Case Study: Using Cadence Palladium for SoC Performance Validation and Analysis
Watch presentation 03:30 PM ARM big.LITTLE Technology for Performance and Energy Savings in Mobile
Watch presentation 05:00 PM Siemens Musings on Advanced Functional Verification with Specman/e in FPGA for Medical Devices
Watch presentation 05:30 PM NXP Layout Dependent Effects - Exploring LDE Analyzer

Wednesday, June 05, 2013
6/5/2013 9:00:00 AM
Session Time Company Topic
Watch presentation 09:00 AM Marvell Low-Power Verification Using CLP
Watch presentation 10:00 AM GLOBALFOUNDRIES A Roadmap for DFM and Physical Design at the Limits of IC Scaling
Watch presentation 10:30 AM Evatronix Must-Have IP for Your SoC: NAND Flash, SlimBus, and USB Controllers
Watch presentation 11:00 AM Tensilica Imaging DSP
Watch presentation 11:30 AM BlueSpec The Best of Both Worlds – Combining Virtual and FPGA-based Prototypes
Watch presentation 12:30 PM GLOBALFOUNDRIES 20nm / 14nm Analog and Mixed-Signal Flow
Watch presentation 01:00 PM Teledyne Lecroy Ubiquitous PCI Express Verification from Simulation through Post-Silicon Development
Watch presentation 02:00 PM SMIC SMIC – Your Foundry Partner for Success in China
Watch presentation 02:30 PM ARM Cortex®-M0 and Cortex-M0+: Tiny, easy and energy efficient processors for mixed signal applications
Watch presentation 03:00 PM Tektronix Efficient PHY Test Approaches for PCIe 3 Compliance and L1 Sub-state Verification
Watch presentation 03:30 PM DINI Group Hardware Solutions for FPGA-based Prototyping
Watch presentation 04:30 PM Cadence and AMD UVM Multi-language with e, SystemVerilog, SystemC, C/C++
Watch presentation 05:00 PM sTec, Inc. Firmware Development and Pre-silicon Verification with FPGA-based Prototyping
Monday, June 03, 2013
Time Company Topic
09:00 AM Marvell Practical ECOs using Conformal ECO
09:30 AM Freescale Implementation of a Multi-threaded 64-bit Power Architecture Core on the RPP, FPGA-based Prototyping System
10:00 AM X-Fab Rapid Adoption of Advanced Cadence Design Flows Using X-FAB's AMS Reference Kit
10:30 AM Texas Instruments Experience Migrating to the UVM
11:00 AM Freescale Best Practices in Verification Planning
11:30 AM ARM AMBA Interconnect IP
12:00 PM Contemporary Verification Consultants Objective Measure of Verification Quality with IEEE 1647 (e) and Incisive HAL
12:30 PM AMD Complementing In-Circuit Emulation with Virtualization for Improved Efficiency, Debug Productivity and Performance
01:00 PM Cisco Managing PCB Constraints with Constraint Manager and SigXplorer
01:30 PM TSMC EDA Flow and Certification
02:00 PM ARM Accelerating Time to Market with ARM Software Development Tools and the Cadence System Development Suite
02:30 PM Broadcom Faster System Bring-up with an Embedded Testbench on Palladium
03:00 PM PMC Implementing Power Gating Flow with CPF
03:30 PM TSMC Custom/AMS Flow
04:00 PM ARM ARM Core Hardening Acceleration using POP IP for Cortex®-A57 and Cortex-A53 (big.LITTLE™ ARMv8 Architecture Designs)
04:30 PM Mobile Semiconductor Statistical Characterization Approach Using Liberate MX with 40nm Low Voltage SRAM
05:00 PM GLOBALFOUNDRIES Innovating Together to Build Exceptional PDKs
05:30 PM ARM ARM Cortex®-A15 Hard Macro and Artisan® POP™ Proof Points

Tuesday, June 04, 2013
Time Company Topic
09:00 AM ARM Low Power Verification of A15 Hard Macro Using CLP
09:30 AM TowerJazz Substrate Noise Isolation Extraction/Model Based on Foundry Measurement Using Cadence Analog Flow
10:00 AM IBM Die Sizing With Cadence Chip Planning System
10:30 AM Silicon Labs Power Mode Verification in Mixed-Signal Chips
11:00 AM Texas Instruments Highly Scalable Multicore ARM A15 Verification with Specman/e.
11:30 AM Forte and Cadence How to Broadly Deploy SystemC High-level Synthesis for Production Hardware Design
12:00 PM IBM An Interoperable Flow with Unified OA and QRC Technology Files
12:30 PM Marvell SoC Interconnect Analysis for Effective Verification, Architectural Exploration and Post-silicon Debug
01:00 PM Texas Instruments Validation Methods of SoC Bus Fabric Performance Using Synthesizable SerDes BFMs on Palladium
01:30 PM ST Microelectronics IPVS and PVS BCD deck support
02:00 PM Methods2Business Towards Formally Proven Embedded System Design with an Unambiguous HW/SW Contract
02:30 PM Tensilica/Cadence Customizable Processor Basics
03:00 PM Freescale Case Study: Using Cadence Palladium for SoC Performance Validation and Analysis
03:30 PM ARM big.LITTLE Technology for Performance and Energy Savings in Mobile
04:00 PM TSMC Quality IP with TSMC
04:30 PM PMC Adoption of PVS at PMC
05:00 PM Siemens Musings on Advanced Functional Verification with Specman/e in FPGA for Medical Devices
05:30 PM NXP Layout Dependent Effects - Exploring LDE Analyzer

Wednesday, June 05, 2013
Time Company Topic
09:00 AM Marvell Low-Power Verification Using CLP
09:30 AM Samsung Cadence-Samsung 14nm FinFET and DFM Collaboration
10:00 AM GLOBALFOUNDRIES A Roadmap for DFM and Physical Design at the Limits of IC Scaling
10:30 AM Evatronix Must-Have IP for Your SoC: NAND Flash, SlimBus, and USB Controllers
11:00 AM Tensilica Imaging DSP
11:30 AM BlueSpec The Best of Both Worlds – Combining Virtual and FPGA-based Prototypes
12:00 PM Oracle Bug Metrics - Predicting the Future
12:30 PM GLOBALFOUNDRIES 20nm / 14nm Analog and Mixed-Signal Flow
01:00 PM Teledyne Lecroy Ubiquitous PCI Express Verification from Simulation through Post-Silicon Development
01:30 PM Freescale Leveraging Fast Models with Palladium XP for performance validation to scale with SoC growth
02:00 PM SMIC SMIC – Your Foundry Partner for Success in China
02:30 PM ARM Cortex®-M0 and Cortex-M0+: Tiny, easy and energy efficient processors for mixed signal applications
03:00 PM Tektronix Efficient PHY Test Approaches for PCIe 3 Compliance and L1 Sub-state Verification
03:30 PM DINI Group Hardware Solutions for FPGA-based Prototyping
04:00 PM Texas Instruments An Inter-Operable Flow with Unified OA and QRC Technology Files
04:30 PM Cadence and AMD UVM Multi-language with e, SystemVerilog, SystemC, C/C++
05:00 PM sTec, Inc. Firmware Development and Pre-silicon Verification with FPGA-based Prototyping