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Cadence on the Agenda
Cadence® technology experts and panelists presented their perspectives on hot industry trends and technology advancements at a wide variety of sessions at DAC 2013.


Session Speaker(s) Co-Presenter, Panelist, Author Day/Time
DAC Workshop: Low-Power Design with the New IEEE 1801-2013 Standard John Biggs, ARM
Sushma Honnavara-Prasad, Broadcom
David Cheng, Cadence
Erich Marschner, Mentor Graphics
Jeffrey Lee, Synopsys
John Biggs, ARM
Sushma Honnavara-Prasad, Broadcom
David Cheng, Cadence
Erich Marschner, Mentor Graphics
Jeffrey Lee, Synopsys
Sunday
1:00 – 5:00
Tutorial: Methodology for Continuous 24x7 Verification and Coverage Hemant Gupta, Cadence
Avi Ziv, IBM
Hemant Gupta, Cadence
Avi Ziv, IBM
Monday
11:00 – 1:00
2:00 – 4:00
5:00 – 7:00
Room: 12ab
A True Interoperable Implementation Solution for Mixed-signal Design Mladen Nizic, Cadence   Monday
10:30
System-Level Power Modeling Standardization Meeting Qi Wang, Cadence   Monday
2:00 – 4:00
Technical Panel: Advanced Node Reliability: Are We in Trouble? Moderator:
Andrew B. Kahng, University of California, San Diego
Panelists:
Vassilios Gerousis, Cadence
Valeriy Sukharev, Mentor Graphics
Martin Saint-Laurent, Qualcomm
Kee Sup Kim, Samsung
Michael (Misha) Khazhinsky, Silicon Laboratories
Tuesday
10:30 – 12:00
Special Session: Goldilocks and the Three Bears of Programmability Chris Rowen, Tensilica Tuesday
10:30 – 12:00
Low Power Verification for Mixed-signal Designs using CPF Qi Wang, Cadence   Tuesday
11:30
Pavilion Panel: Organizational and Management Solutions to the Verification Crisis Moderator: Mike Stellfox, Cadence Panelists:
Alan Hunter, ARM
Neeta Ganguly, Intel
Scott Runner, Qualcomm
Tuesday
1:30 – 2:30
Poster Session: Smarter, Greener Systems with Superior Productivity and Increased Predictability Using Dynamic Power Analysis Raghu Binnamangalam, Cadence Authors:
Jingbo Gao, Cadence
Bing Zhu, Cadence
Tuesday
12:30 – 1:30
Poster Session: Automation of Power Intent through CPF for Low-Power Designs Jose Flores, Texas Instruments Authors:
Kaijian Shi, Cadence
Anthony Hill, Texas Instruments
Tuesday
12:30 – 1:30
Poster Session: Macro Modeling-Based, Layout-Dependent Effect Aware Design Flow Pei Yao, GLOBALFOUNDRIES Authors:
Philippe Hurat, Cadence
Ajish Thomas, Cadence
Rais Huda, GLOBALFOUNDRIES
Grace Gao, Rambus
Joe Louis-Chandran, Rambus
Tuesday
12:30 – 1:30
Poster Session: A Sequential Equivalence Checking “App” Using Off-the-Shelf Formal Analysis Tools Darrow Chu, Cadence Authors:
Darrow Chu, Cadence
Amy Yen, NVIDIA
Tuesday
12:30 – 1:30
Paper Session: Litho is Hot Bei Yu, University of Texas at Austin Authors:
Kun Yuan, Cadence
Bei Yu, University of Texas at Austin
Jhih-Rong Gao, University of Texas at Austin
David Z. Pan, University of Texas at Austin
Wednesday
9:00 – 10:30
System Level Low Power Verification using Palladium   Author: Qi Wang, Cadence Wednesday
10:30
Poster Session: SOC Interconnect Analysis for Effective Verification, Architectural Exploration, and Post-Silicon Debug Ravi Kalyanaraman, Marvell Authors:
Nick Heaton, Cadence
Bill Watt, Cadence
Lalitha Bagepalli Shivaprakash, Marvell
Kumaril Bhatt, Marvell
Lilian Tran, Stanford University
Wenjia Liu, University of Michigan
Wednesday
12:30 – 1:30
Poster Session: Placement Dependent Variability Assessment of Standard Cell Libraries Concetta Riccobene, LSI Authors:
Philippe Hurat, Cadence
Huiyuan Song, Cadence
Wei Xu, Cadence
Robert C. Armstrong, LSI
Kausar Banoo, LSI
Bob Davis, LSI Bob Davis, LSI
Rich Laubhan, LSI
Concetta Riccobene, LSI
Wednesday
12:30 – 1:30
Poster Session: Power Estimation in Low-Power Microcontrollers and Mixed-Signal Designs Qi Wang / Cadence Authors:
Joseph Yiu, ARM
Qi Wang, Cadence
Pete G. Hardee, Cadence
Wednesday
12:30 – 1:30
Designer Track: Using Virtual Platforms for Firmware Verification Jason Andrews, Cadence Authors:
James Pangburn, Cadence
Jason Andrews, Cadence
Thursday
1:30 – 3:00
Technical Panel: Analog Design with FinFETs: “The Gods Must be Crazy!” Moderator: Ron Wilson, Altera Panelists:
Anirudh Devgan, Cadence
Scott Herrin, Freescale
Navraj Nandra, Synopsys
Eric Soenen, TSMC
Thursday
1:30 – 2:30
Paper Session: netShip: A Networked Virtual Platform for Large-Scale Heterogeneous Distributed Embedded Systems YoungHoon Jung, Columbia University Authors:
Michele Petracca, Cadence
YoungHoon Jung, Columbia University
Luca P. Carloni, Columbia University
Jinhyung Park, Thing Daemon, LLC
Thursday
3:30 – 5:30