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Breakfasts and Luncheons
Cadence, our customers, and our ecosystem partners shared their expertise and project experiences during compelling panels and presentations throughout the week of DAC. Topics included timing signoff and closure, system-to-silicon verification, challenges in FinFET deployment, and verifying coherent interconnects. For more information about these special events, send an email to events@cadence.com.
Monday, June 03, 2013
11:30 AM - 01:30 PM
Has "Timing Signoff Innovation" Become an Oxymoron? What Happened and How Do We Fix It?

This session has reached maximum capacity. Registration is now closed.

In this panel fielded by leading-edge technologists and venture capitalists, we will discuss the technology advances, or lack thereof, in the area of timing signoff. Timing signoff and closure is becoming the largest pole in the design flow tent with the increase in MMMC timing analysis views, lack of integrated signoff closure tools, and increasing variation factors. Each panelist will provide their insight into what’s needed from the EDA industry, academia, and users to ensure that innovation keeps pace with design needs.

Tuesday, June 04, 2013
08:00 AM - 10:00 AM
The Cadence System-to-Silicon Verification Breakfast

This session has reached maximum capacity. Registration is now closed.

Join us for a free breakfast to learn how next-generation system and SoC verification offerings from Cadence accelerate your system integration and reduce time to market. Learn about the newest capabilities of the Cadence System Development Suite, including Virtual System Platform virtual prototyping, Incisive® advanced verification, Palladium® acceleration and emulation, Rapid Prototyping Platform FPGA-based prototyping, and the Verification IP catalog, which adds new communication protocols and now supports acceleration and emulation. Listen to discussion about the latest methodologies for advanced verification and example applications from key Cadence customers. Be sure to bring your toughest questions for our experts panel.

Moderator:
Brian Fuller

Panelists:
Mihir Pandya, Freescale
Avi Ziv, IBM
Alex Starr, AMD
Mike Stellfox, Cadence

11:30 AM - 01:30 PM
Panel: FinFETs - Challenges in Deployment

This session has reached maximum capacity. Registration is now closed.

Cadence will host a panel of industry leaders discussing the challenges in deploying advanced node designs including FinFETs. Panelists will debate issues around process development, optimization interplay, and performance, power and density trade-offs. Participants include leaders from such companies as TSMC, ARM, Texas Instruments and Cadence. Join us for an informed and lively discussion, served with a delicious lunch. Doors open at 11:30am.

Moderator: Brian Fuller

Panelists:
John Heinlein – ARM
Anthony Hill – Texas Instruments
Suk Lee – TSMC
Vinod Kariat – Cadence

Wednesday, June 05, 2013
08:00 AM - 10:00 AM
Unique challenges posed by coherent SoC interconnects: verifying hardware-managed coherency and analyzing performance

This session has reached maximum capacity. Registration is now closed.

At this Cadence-hosted breakfast panel, ARM will describe the advantages of coherent SoC interconnects as well as the ARM specifications and IP products that implement them. Cadence will outline the challenges of verifying coherent interconnects and explain the verification IP products that address those challenges. Tools and approaches for characterizing interconnect performance and finding performance bottlenecks will also be presented.

Speakers:
William Orme – ARM
Avi Behar – Cadence
Stewart Penman – Cadence



Thursday, June 05, 2014
09:00 AM - 10:00 AM
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