Technology Luncheons and Breakfasts
During the following events, Cadence, our customers, and our ecosystem partners shared their project experiences and product successes in the critical areas of advanced node design, custom IC design, mixed-signal design and verification, and system development. If you are interested in finding out more about any of the following events, send an email to firstname.lastname@example.org
Monday June 4
Overcoming Variability and Productivity Challenges in Your High-Performance, Advanced Node, Custom/Analog Design
Speakers: Francois Lemery, CAD Project Manager, STMicroelectronics, Vinod Kariat, Fellow, Cadence, Thomas Volden, Architect, Cadence
At advanced nodes, new design and layout rules, design constraints (like device matching), and variability introduce challenges that require a paradigm shift in how you manage the design and manufacturing process. If you’re a custom/analog engineer looking to shorten design time from specs to GDSII, this luncheon is for you. You’ll see a comprehensive flow that you can use today to optimize circuit performance without over-designing and to reduce total design time. Cadence technology experts will walk you through a real design example and demonstrate the steps from specification to layout to signoff. You’ll see proven technologies that can help you manage and avoid layout-dependent effects. Discover why the Virtuoso platform, with its 22-year history of tens of thousands of tapeouts, leads the industry in custom/analog design, verification, and signoff.
Tuesday June 5
Addressing Hardware/Software Co-Development, System Integration, and Time to Market
Speakers: LSI Corp, AMD, and Cadence
Join us for a complimentary breakfast to learn how next-generation system and SoC verification offerings from Cadence can accelerate your system integration process, optimize hardware/software co-development, and ultimately reduce time to market. You’ll learn about the latest enhancements to our System Development Suite and Verification IP (VIP) Catalog. You’ll also see example applications and hear about shared experiences from LSI Corp and other users. A expert panel of guests and Cadence technologists will answer your questions about system-level development challenges.
Wednesday June 6
The Path to Yielding at 2(x)nm and Beyond
Speakers: Gary Patton, VP Semiconductor R&D, IBM, Chi-Ping Hsu, Sr. VP R&D, Cadence, Dipesh Patel, Deputy GM, Physical IP, ARM, KM Choi, VP IDC, Samsung, Mojy Chian, Sr. VP Design Enablement, GLOBALFOUNDRIES
At advanced nodes there are disruptive design and manufacturing discontinuities that must be understood and handled to ensure successful silicon yields. Moving to 28/20nm and down to 14nm process technologies calls for a paradigm shift in the way ICs are designed and manufactured. This panel explores the challenges of process and IC design at advanced nodes, and ramping to volume production. We will examine these challenges from foundry, EDA, and customer perspectives, sharing our combined experiences and recommendations on how to ensure a faster, more predictable path to yielding at 2(x)nm and beyond.