Accelerate system integration and reduce time to market using our suite of connected platforms for virtual prototyping, RTL simulation, emulation/acceleration, and FPGA-based prototyping—now featuring in-circuit acceleration, combining the best of simulation acceleration and in-circuit emulation. Functional Verification
Giga-gate SoC verification requires a strong mix of methodology served by high-performance automation. See our new work flows that address the top pain-points in customer surveys: low-power verification, advanced debugging, ubiquitous formal analysis, and automated planning/management to track progress and reach closure across digital, firmware, AMS, and assertion/formal domains. Verification IP
With support for 40+ complex protocols and 6,000 memory models covering 85 manufacturers, our Verification IP (VIP) Catalog provides unparalleled support for new and emerging protocols that define mobile platforms and interfaces behind the expanding cloud infrastructure. Find out how our advanced VIP—production-proven on thousands of designs with 500+ customers—can help you. Design IP
Get an overview of our high-performance, low-power, and highly configurable portfolio of Design IP. Our focus on advanced capabilities and mass configurability enables customers to utilize IP as a way to differentiate their designs; our focus on quality reduces risk and speeds time to market. 20nm / 3D-IC Design
New-generation, high-speed, advanced node designs promise higher bandwidth and lower power chips. But going to 20nm introduces new discontinuities to design and manufacturing. See highlights of a methodology to optimize power, performance, and area for 20nm, 3D-IC chip today. Examples of production-proven silicon will help you gain clarity to succeed at advanced nodes. Mixed-Signal / Low-Power Design
The Cadence Mixed Signal Solution can help you verify low-power intent in a mixed-signal design. Perform mixed-signal simulation while using CPF to manage power modes and signal crossings between power domains. Automatically generate CPF macro model for custom or mixed-signal block and apply static methods for faster low-power verification.