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Home > DAC 2012 > Conference Speakers

Conference Speakers
Cadence technology experts and panelists discussed industry trends and technology advancements at a wide variety of sessions at DAC 2012.

Sunday, June 3
Workshop
DAC Workshop on More than Moore Technologies
Cadence Speaker: Samta Bansal
Time: 8:30 AM — 6:00 PM
Location: 309

Monday, June 4
Tutorial 2: Enough Talk! Practical Approaches to 3D-IC - TSV/Silicon Interposer and Wide I/O Implementation From People Who Have Been There and Done That
Cadence Speaker: Marc Greenberg
Time: 8:30 AM — 10:30 AM, repeated at 11:30 AM – 1:30 PM, and again at 3:30 PM to 5:30 PM
Location: 302

Tutorial 4: Understanding and Overcoming Patterning-Induced Design Challenges in the 20nm and 14nm Technology Nodes
Cadence Speaker: Vassilios Gerousis
Time: 8:30 AM — 10:30 AM, repeated at 11:30 AM – 1:30 PM, and again at 3:30 PM – 5:30 PM
Location: 307

Tutorial 5: Analog and Mixed-Signal Design at Advanced Process Nodes
Cadence Speakers: Jim McMahon, Stacy Whiteman, Fang-Cheng Chang
Time: 8:30 AM — 10:30 AM, repeated at 11:30 AM – 1:30 PM, and again at 3:30 PM – 5:30 PM
Location: 306

Co-located Conference
Si2 Round-Up @ DAC: Standards in Action
Cadence Speaker: Keith Felton, Gilles Lamant / Li Ting / Ted Paone
Time: 9:00 AM — 6:00 PM
Location: 301

Tuesday, June 5
Panel
System Models: Does One Size Fit All?
Cadence Speaker: Stuart Swan
Time: 1:30 PM — 3:00 PM
Location: 305

Paper
Reliability: From Atoms to 3D
Cadence Speaker: Xuchu Hu
Time: 1:30 PM — 3:00 PM
Location: 300

Additional Meetings
IEEE CEDA Presents: Digital Analog Design
Organizer: Joel Phillips
Time: 12:00 PM — 2:00 PM
Location: 303

User Track Poster Session
2U.1 – an RTL Developers Guide to the HLS Galaxy
Cadence Speaker: Sergio Ramirez
Time: 12:30 PM — 1:30 PM
Location: 105 (Exhibit Floor)

User Track Poster Session
2U.16 – Real Value Modeling Enables Metric Driven Verification of Mixed Signal Design
Cadence Speakers: Kishore Karnane, Walter Hartong
Time: 12:30 PM — 1:30 PM
Location: 105 (Exhibit Floor)

User Track Poster Session
2U.17 – Verification of Massive Advanced Node SoCs
Cadence Speaker: Adam Sherer
Time: 12:30 PM — 1:30 PM
Location: 105 (Exhibit Floor)

User Track Poster Session
4U.1 – 40nm and 28nm Variability-Aware Digital Design
Cadence Speakers: Philippe Hurat, Chris Pitchford
Time: 4:00 PM — 6:00 PM
Location: 106

DAC 2012 Management Day
Cadence speaker: Pankaj Mayor
Time: 10:00am – 4:00pm
Location: 309


Wednesday, June 6
Panel
High-Level Synthesis Production Deployment: Are We Ready?
Cadence Speaker: Mark Warren
Time: 9:00 AM — 10:30 AM
Location: 305

Paper
Design, the Next Generation: From Routing to Capturing Design Expertise
Cadence Speaker: Yanheng Zhang
Time: 1:30 PM — 3:00 PM
Location: 300

User Track Poster Session
6U.32 – Impact of Lithography and Stress n 28nm Design Performance
Cadence Speaker: Philippe Hurat
Time: 12:30 PM — 1:30 PM
Location: 105 (Exhibit floor)

Hosted Luncheon: Accellera Systems Initiative Rolls Out The Unified Coverage Interoperability Standard
Time: 12:00 PM — 1:30 PM
Location: 250

North American SystemC User's Group Meeting
Cadence Speaker: Stuart Swan
Time: 2:00 PM – 6:00 PM
Location: 250 and 262

IP Standardization – What’s in it for Me?
Cadence Speaker: Adam Traidman
Time: 2:30 PM
Location: Duolog Booth #1520

Thursday, June 7
Panel
Is 3D Ready for the Next Level?
Cadence Speaker: AJ Incorvaia
Time: 9:00 AM — 10:30 AM
Location: 305

The ESL Hotspot – Where Software and Hardware Meet
Cadence Speaker: Frank Schirrmeister
Time: 11:30 AM – 1:00 PM
Location: Gateway Ballroom 104

User Track Poster Session
10U.2 – SyMIX – Model Crossover between Simics and SystemC/TLM Virtual Systems Platforms
Cadence Speakers: Hans-Peter Loeb, Christian Sauer
Time: 1:30 PM — 3:00 PM
Location: 303