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Getting a Jumpstart on 20nm



When a major technology disruption like designing and implementing at the 20nm node confronts our industry, we look to industry leaders to help point the way forward. At DAC, Cadence hosted the luncheon panel, "Getting a Jumpstart on 20nm." The luncheon featured a lively, informative discussion among industry luminaries from across the electronics industry on the challenges and opportunities facing us when designing and implementing at the 20nm node.

Media coverage:

Richard Goering View blog»

Steve Leibson View blog»

Kevin Morris View article»

Abstract:
Design and implementation at 20nm is uncovering unprecedented challenges that are shaking the very core of electronic design. Integrating baseband into the software-configurable, multi-core, application processor of tomorrow, while worrying about how new devices will change the way that we design and address power from architecture to silicon in a memory/bandwidth-enabling 3D-IC, is but one reality that we have to address today. This panel brings together IP providers, semicos, and EDA vendors to discuss the challenges and approaches that need to be considered when designing and implementing at the 20nm node.

Moderator
Jim Handy, Objective Analysis - Analyst

Panelists
  • Chi-Ping Hsu - Cadence, Senior Vice President, Silicon Realization
  • Simon Segars - ARM, Executive Vice President and General Manager, Physical IP
  • Ana Hunter - Samsung, Vice President, Foundry Services
  • Philippe Magarshack - STMicroelectronics, Vice President for Design Automation and Libraries, Central Research and Development Group


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