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Cadence Events
Silicon Realization Luncheon

Tuesday, June 15
11:30am – 1:00pm
Anaheim Convention Center, Level 3
Room 304CD

32- and 22-nm complexities are upping the ante for leading-edge chip designers. At these advanced nodes, Silicon Realization requires the creation and integration of extremely large, complex analog and mixed-signal IP blocks into ICs and SoCs. Engineers need to hit aggressive design targets with fewer resources and narrower market windows. The productivity and profitability gap is thwarting the path to Silicon Realization. To stay competitive, IP vendors, IC and SoC companies, and foundries need a new way forward.

In a dynamic panel moderated by Cadence CMO John Bruggeman, experts from Cadence, GLOBALFOUNDRIES, Texas Instruments, Broadcom, and Rapid Bridge will discuss how to get from design concept to silicon as quickly and cheaply as possible, while retaining the high quality that end consumers demand. Find out how successful engineering teams are designing extremely complex functions at ultra-low-power and high speeds, while also optimizing yield and limiting package costs.

Panelists:
Moderator: John Bruggeman, Senior Vice President and Chief Marketing Officer, Cadence
Speakers:
  • Sandy Mehndiratta, Group Director, Cadence
  • Benny Malek-Khosravi, CTO, Rapid Bridge
  • Jacob Rael, Broadcom
  • Steve Jones, Texas Instruments
  • Subramani Kengeri, Vice President, GLOBALFOUNDRIES
Agenda
11:30 - 11:45am Complimentary lunch is served
11:45 - 12 noon Keynote speech
12:00 - 12:30pm Panel speakers (5 minutes each)
12:30 - 1:00pm Moderated Q&A session and closing remarks
 

Management Day

Tuesday, June 15, 2010
10:30am – 6:00pm
Anaheim Convention Center
Room 204C
Reception: 5:30pm – 6:00pm

Session 1:
Tuesday 10:30am-12:00pm
Presentation Session
Title: Decision Making for Complex ICs

Session Chair: Richard Goering, Cadence
Session Organizer: Yervant Zorian, Virage Logic

Abstract:
Moving to new semiconductor technology nodes for complex ICs can significantly affect the choices of design flow, methodologies and suppliers. The session will cover the challenges of complex chip design and present corresponding management decision criteria that allow managers to make the right choices from a pool of alternate options. This session feature presentations by managers representing independent device manufacturers (IDMs), fab-light ASIC providers, and fabless companies.

Speakers:
  • Ken Wanger, Vice President of Engineering, PMC Sierra
  • Ty Garibay, Senior Director, OMAP IC Design, Texas Instruments
  • Jitu Khare, Director Central Engineering, AMCC
More information »

 

Embedded SOC Enablement Day

Thursday, June 17, 2010
9:00am – 6:00pm
Anaheim Convention Center
Room 303A

The Embedded / SOC Enablement Day is a day-long track dedicated to bringing industry stakeholders together in one room to shed light on where embedded SOC design is headed. SOC design engineers, embedded systems designers, IP integrators, FPGA designers, investors, foundry representatives and the analysts will be on hand in this new forum to hear from industry leaders and network with each other.

Each session will be comprised of four presentations followed by a discussion panel, where key senior managers of today’s design ecosystem will discuss the emerging trends and share their vision.

Session 1:
Tuesday 9:00am - 11:00am
Presentation Session
Title: Enabling Tomorrow's Complex SOCs

Session Chair: Peggy Aycinena, EDA Confidential
Session Organizer: Yervant Zorian, Virage Logic

Invited Keynoter:
  • Gadi Singer, Vice President and General Manager, SoC Enabling Group, Intel
Presenters:
  • Sami Issa, Executive Director, Advanced Technology Investment Company (ATIC)
  • Alex Shubat, President and Chief Executive Officer, Virage Logic
  • John Bruggeman, Chief Marketing Officer, Cadence
Abstract:
The embedded processor based System-on-Chip market is being hotly contested right now as companies vie for their piece of this high stakes segment of the semiconductor industry. This session is comprised of presentations from leading SoC enabling sectors including embedded processors, semiconductor investments, IP and EDA providers.

More information »

 
Silicon Realization Lunch Panel
Hosted by Cadence on
Tuesday, June 15.
Demo Suites
Sign up for demos and choose from a variety of live product presentations.
EDA360 Idol at the Denali Party
Monday June 14 at the
House of Blues.
Sponsored by Cadence
Cadence is a Platinum exhibitor and is sponsoring Management Day on Tuesday, June 15.
ChipEstimate.com IP Talks! Visit us at the ChipEstimate.com booth #521.
EDA360 – The Way Forward for Electronic Design Download the Vision Paper.