Choose from a variety of product and flow demonstrations that highlight The Way Forward for Electronic Design. The Cadence demo suites offer an in-depth look at the latest in digital design and implementation, custom/analog design, metric-driven verification, mixed-signal and low-power design, packaging and board solutions, and systems development. You’ll also hear more about the recently announced Open Integration Platform and how the entire mix delivers Silicon, SoC, and System Realization solutions for the electronics industry.
Online registration is now closed. Onsite registration in the Cadence booth opens Monday, June 14 at 9 AM.
Digital Design: Delivering Silicon Realization with Predictable Design Closure
This session highlights the Cadence Encounter digital IC design flow from RTL-to-GDSII, focusing on planning, design, integration and optimization. The session illustrates how to improve productivity starting with chip planning, and shares further benefits of moving to higher levels of design abstraction from RTL to transaction-level modeling (TLM), improving quality with physically aware multi-objective optimization, and achieving deterministic design closure by performing up front analysis, verification, and test. The session outlines a methodology for building and assembling IP blocks and ensuring the readiness of the TLM/RTL, timing constraints, and power constraints for chip-level integration. Presenters will further illustrate a path to implementation, starting by bringing physical awareness into synthesis along with ECO technology that minimizes changes later in the flow, to enable predictable design closure.
Digital Implementation: Delivering Silicon Realization Productivity for Breakthrough Digital Implementation
This session highlights the Cadence Encounter digital IC design flow from RTL-to-GDSII, focusing on big leaps forward in physical implementation and signoff. Prototype your designs using advanced abstraction models to implement billion-gate designs with the utmost in performance and quality of results. Leverage the scalable Encounter multi-core backplane and “in-design” signoff analysis and DFM to achieve faster design convergence and design time. Learn how to tackle your most advanced low-power and mixed-signal design challenges in a fraction of the time. And, check out how the latest version of the Encounter platform allows you to handle advanced double-patterning, 3D IC/TSV, silicon-on-insulator (SOI), and system-in-package (SiP) challenges.
Custom/Analog - Design/Verification: Delivering Silicon Realization Productivity for Breakthrough Custom Design and Simulation
This presentation highlights the Cadence Virtuoso custom IC design flow, focusing on design, simulation, and preparing the design for fast physical implementation. See how the latest version of the Virtuoso platform allows you to create, simulate, and analyze your custom design quickly and efficiently, while exploring and optimizing the design for yield and ensuring the design moves to the final physical implementation phase with the utmost in ease and confidence.
Custom/Analog - Implementation: Delivering Silicon Realization Productivity for Breakthrough Custom Implementation and Verification
This presentation highlights the Cadence Virtuoso custom IC design flow, focusing on physical implementation and final verification. See how to tackle the most complex implementation problems easily and effectively by harnessing built-in acceleration for placement, routing, and verification and by diagnosing IR drop and electromigration issues in the process. The session will also outline the new design, methodology, and manufacturing requirements that accompany the latest advanced process nodes, and how to address these requirements with confidence prior to tapeout.
Delivering Predictable Silicon Realization with UVM and Metric-Driven Verification
This session describes a unique approachA Universal Verification Methodology (UVM) and metric-driven verification (MDV) flow which automates the plan, construct, execute, measure & analyze flow for productive and effective verification. Specific new features presented include planning links to SoC Realization and System Realization, construction of automated verification environments with Verification IP and the UVM standard, multi-core simulation and formal analysis to improve performance. You will also learn more about analysis of metrics from simulation and formal analysis, and traditional verification metrics to use in project management tools. The combination of these capabilities enables cost-effective and predictable verification, ensuring that project objectives are achieved.
Delivering Silicon Realization for the Next Generation of Mixed-Signal SoCs
For today’s mixed-signal SoCs to be profitable, semiconductor companies have to meet a combination of speed, low-power, and yield specifications that set the bar at a whole new level. To meet market demand, companies must also deliver these SoCs under increasingly aggressive schedules. Cadence will discuss a methodology for realizing mixed-signal designs that provides cross-domain interoperability, allows analog and digital designers to improve their productivity throughout the chip design, verification, and implementation process, and ensures that companies will meet their product specifications and schedule targets.
Delivering Silicon Realization for Advanced Low-Power Design
In this suite presentation, Cadence will showcase the most proven and capable flow for low-power design. The session will demonstrate advanced low-power design methodologies enabled in either Common Power Format (CPF) or Universal Power Format (UPF) using the Interoperability Guide for Power Format Standards.
Delivering Silicon Realization with IC Packaging and Co-design
In this suite presentation, Cadence will showcase its market-proven IC packaging solutions and how they are used to help semiconductor teams meet cost and schedule demands. Through a combination of advanced package design techniques, optimized chip-package-board implementation, and system-level analysis of timing, power, and signal integrity, Cadence enables IC and package design teams to cooperatively meet today’s dynamic and evolving IC packaging challenges.
Cadence Open Integration Platform
As the driver behind SoC Realization, the Cadence Open Integration Platform provides an integration-centric approach to design and is built on a foundation of integration-optimized IP to accelerate SoC development and reduce costs. This presentation will present the Cadence Open Integration Platform and provide a comprehensive overview of what it takes to address the key steps toward successful SoC Realization, focusing on the deivery of integration-optimized IP such as SuperSpeed USB 3.0.
System Development with Scalable Performance, Improved Productivity and HW/SW Integration
In order to increase productivity and shrink time to market, semiconductor companies are forced to automate their IP creation process and deliver an integrated hardware-software platform to their OEM customers. In the demonstration Cadence will showcase its system development solutions that includes its TLM-driven design and verification capabilities, system modeling methodologies, as well as a look at validation of the system using the industry 1st high-performance Verification Computing Platform. The developing systems ecosystem will be also highlighted in this session.
| Silicon Realization Lunch Panel
Hosted by Cadence on
Tuesday, June 15.
| Demo Suites
Sign up for demos and choose from a variety of live product presentations.
| EDA360 Idol at the Denali Party
Monday June 14 at the
House of Blues.
| Sponsored by Cadence
Cadence is a Platinum exhibitor and is sponsoring Management Day on Tuesday, June 15.
ChipEstimate.com IP Talks!
Visit us at the ChipEstimate.com booth #521.
EDA360 – The Way Forward for Electronic Design
Download the Vision Paper.