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Cadence Events
Tuesday, July 28, 2009
11:30 AM – 1:30 PM
Moscone Convention Center
Rooms 306 & 308

11:30am Registration opens
11:45am Panel: "Are SystemC- and TLM-Driven Design Ready to Replace RTL?"

Sponsors: Cadence, Calypto, and Forte

Join Cadence, Calypto, and Forte Design Systems for an informative System-level luncheon at DAC. This event includes a mix of presentations and an informative panel discussion intended to stir up debate on how SystemC and TLM-driven design techniques have evolved to a point where they are mounting a credible challenge to traditional RTL-based design. Hear for yourself from the companies driving this evolution as they describe the productivity gains and real-world challenges they face as they migrate to this new approach.

(Lunch will be provided at this event.)

Moderator: Dr. Mark S. Johnstone, Chief Technologist, Freescale

Panelists:
  • Michael McNamara, VP & GM Systems Software Group,
    Cadence Design Systems
  • Tom Sandoval, CEO, Calypto Design Systems
  • Sean Dart, CEO, Forte Design Systems
  • Laurent Ducousso, Engineering Director, ST Microelectronics
  • Yutetsu Takatsukasa, Technical Engineer, HD Lab, Inc.
  • Jen-Chieh Yeh, Technical Engineer, STC, ITRI
1:30pm Luncheon concludes

Online registration is now closed. Please register on site at booth #3751 (North Hall).

 
Wednesday, July 29, 2009
12:30 PM – 2:00 PM
Moscone Convention Center
Rooms 306 & 308

12:30pm Registration opens
1:00pm Panel: "Are You Ready for 32nm?"

Sponsors: ARM, Cadence and Common Platform

With 32nm and 28nm setting a new bar for leading edge chip designs, are you ready? Reducing the risk in designing for advanced manufacturing process requires an industry collaboration. ARM, Cadence and Common Platform partners, Chartered, IBM, and Samsung have been working together to develop tools, design flows, and IP capabilities for 32/28nm Common Platform technology. If you are considering designing at the 32/28nm node, join us for an in-depth discussion on enablement of the industry’s first HKMG technology offering. Common Platform partners will describe the 32/38nm High-K Metal Gate process which enables continued technology scaling in the tradition of Moore’s Law. Technologists from ARM and Cadence will detail their results-to-date in integrating advanced design flows and IP on the Common Platform technology.

(Lunch will be provided at this event.)

Moderator: Ana Molnar Hunter, Vice President of Foundry,
Samsung Semiconductor, Inc.

Panelists:
  • Dr. Rob Aitken, Fellow, Research & Development, ARM
  • Dr. Vassilios Gerousis, Senior Architect,
    Cadence Design Systems
  • Dr. Jaga Jagannathan, Director, 32/28 Technology Productization,
    IBM Semiconductor R&D Center
2:00pm Luncheon concludes

Online registration is now closed. Please register on site at booth #3751 (North Hall).

 
Demo Suites
Sign up for demos and choose from a variety of live product and flow demos.
Sponsored by Cadence
Cadence is sponsoring Management Day on July 28 and User Track on July 28-30.
ChipEstimate.com IP Talks! Learn more in the IP Talks! video and visit us at the ChipEstimate.com booth #1100.
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