|
Demo Suites
Choose from a variety of live product and flow demonstrations. In the Cadence demo suites, you’ll see the latest advances in system-level design, transaction-level modeling, enterprise verification, power-efficient design, advanced node adoption, model-based design for manufacturing, and mixed-signal solutions. Cadence experts will demonstrate the productivity gains and risk mitigation benefits that these advanced technologies have to offer.
SystemC TLM-Driven Design and Verification Flow
The RTL-based design paradigm is now more than 20 years old. Many experts believe that, over the next decade, SystemC/transaction-level modeling (TLM)-based design will replace RTL, enabling 2-10x productivity increases for engineers in design and verification tasks across the board. During the past several years, Cadence has been driving this evolution with new breakthrough technologies such as C-to-Silicon Compiler and Incisive Software Extensions, as well as SystemC/TLM extensions to its mainstay SoC verification solutions, Incisive Enterprise Simulator and the Palladium System.
Using design examples featuring ARM Cortex A9 and AXI IP components, this demo will showcase the full Cadence SystemC/TLM-based flow for SoC front-end design and verification. It starts with C-to-Silicon Compiler for micro-architecture exploration and RTL development, then Incisive Software Extensions/Incisive Enterprise Simulator/Simics for virtual prototyping and software development, and finally Palladium technology for full-system verification/validation. This demo will also highlight the critical roles of Cadence metric- and coverage-driven verification techniques running on top of Open Verification Methodology (OVM) verification IP and design-planning tools working throughout the flow to ensure SoC quality and predictability. The flow will show the productivity benefits of IP/VIP reuse.
Featured products: C-to-Silicon Compiler, Incisive Software Extensions and Incisive Enterprise Simulator, Incisive Enterprise Manager, Incisive Xtreme System and Incisive Palladium system.
Online registration is now closed. Please register on site at booth #3751 (North Hall).
Low Power for All: Reduce Power While Reducing Risk
Power efficiency is now a serious consideration for all designs, and no longer limited to battery powered devices. One of the greatest challenges when adopting low-power is understanding its benefits, risks and impact on your specific design. The Cadence Low-Power Solution provides a highly automated and predictable environment and methodology for design, verification, and implementation of digital and mixed-signal designs. It spans early system-level exploration through physical design and signoff, and leverages comprehensive exploration, estimation and analysis technology throughout including the ability to incorporate real-world hardware and software execution data. This demo will show you how the Cadence Low-Power Solution enables low power for all designs.
Featured products: Cadence Chip Planning System, C-to-Silicon Compiler, Incisive Enterprise Simulator, Incisive Enterprise Manager, Incisive Formal Verifier, Incisive Software Extensions, Incisive Palladium System, Encounter Conformal Low Power, Encounter RTL Compiler, Encounter Test, Encounter Digital Implementation System, Encounter Power System, Encounter Timing System, and Virtuoso AMS Designer.
Online registration is now closed. Please register on site at booth #3751 (North Hall).
Accelerate Your Advanced Node Design
At advanced process technology nodes, even slight perturbations in the design flow can cause dramatic swings in the design integrity; designers face a predictability crisis. Cadence can help accelerate your migration to advanced node design by mitigating design risk, preventing downstream problems, eliminating re-spins, and maximizing yield—resulting in differentiation for your end products. The Cadence Advanced Node Design Solution provides a complete, consistent, and converging flow across the Encounter Digital Implementation and Virtuoso Custom Implementation solutions to address DFM and variability effects (lithography, CMP, stress, and process variations) in the early stages of the design flow.
In this demo, you will see how the Cadence solution provides a 10x productivity gain over traditional DFM-closure solutions by integrating model-based design-for-manufacturing and statistical technology in a comprehensive prevention-analysis-repair flow. Experience the patented interconnect optimization technology with a unique 3D shape- and space-based approach to model, analyze, and optimize true shapes and intervening physical spaces. This capability affords the best combination of precision and flexibility when optimizing interconnects using tiered foundry and recommended design and manufacturing constraints, leading to the highest yield and best quality of silicon.
Featured products: Virtuoso technologies, Encounter Digital Implementation System, Cadence DFM technologies (Litho Physical Analyzer, Litho Electrical Analyzer, CMP Predictor, QRC Extraction), and Cadence Chip Optimizer/YieldPlus.
Online registration is now closed. Please register on site at booth #3751 (North Hall).
It’s a Mixed-Signal World
Mixed-signal design issues are no longer the exclusive domain of analog/mixed-signal ICs. Most SoCs at 65nm and below contain a significant amount mixed-signal IP. Fifty percent of re-spins of these mixed-signal SoCs are due to inefficiencies in mixed-signal integration and verification methodology. Moreover, mixed-signal IP does not scale well to nanometer process technologies, leading to alternate implementation vehicles such as 3DIC and SiP. The Cadence Mixed-Signal Solution provides a highly automated design, verification, and implementation methodology for mixed-signal ICs, SoCs, and SiPs to enable advanced verification and integration capabilities that significantly increase predictability and productivity. This demo will show you the industry’s leading mixed-signal solution based on 20 years of experience.
Featured products: Incisive Enterprise Verification, Virtuoso AMS Designer, Virtuoso 6.1 platform technologies, Encounter Digital Implementation System, Cadence SiP RF Architect, Cadence SiP RF Layout.
Online registration is now closed. Please register on site at booth #3751 (North Hall).
Enterprise Verification: Reducing Risk with Comprehensive Metrics
Functional verification remains the dominant task in most chip development projects, introducing uncertainty into the schedule and increasing the risk of bugs escaping into silicon. The Cadence Enterprise Verification Solution is the remedy for these challenges. Starting with an executable verification plan, every automated step reports a set of unified metrics against the plan to assess progress toward verification closure; these metrics can be rolled up to track verification progress at all levels of project tracking. This provides a much more predictable verification process, from block to chip to system, increasing team productivity while improving design quality.
Verification technologies encompassed by this solution include analog, digital, and mixed-signal simulation, hardware acceleration and emulation, equivalence checking, formal analysis and checking, low-power verification, and a wide variety of design and verification checks (coding rules, design style, design constraints, low power, and clock domain crossings). The entire verification environment is built on the multi-language Open Verification Methodology (OVM), enabling the most advanced technologies and leveraging extensive verification IP reuse. Only the Cadence Enterprise Verification Solution has the breadth and depth to handle the complete functional verification needs of today’s most complex designs, along with verification services to optimize project predictability, productivity, and quality.
Featured products: Encounter Conformal Equivalence Checker, Encounter Conformal Constraint Designer, Incisive Enterprise Simulator, Incisive Enterprise Specman technology, Incisive Enterprise Manager, Incisive Formal Verifier, Incisive Verification IP, Incisive Xtreme System, and Incisive Palladium System.
Online registration is now closed. Please register on site at booth #3751 (North Hall).
|
|
|