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Cadence Exhibits
Ecosystem Collaboration for Customer Success
Booth 4300 (North Hall)
Collaboration across the electronics industry is essential to ensure customer success. Learn how industry leaders ARM, Cadence and TSMC work together to facilitate interoperability and optimize handoffs throughout the entire design chain. Hear success stories of collaborative efforts from customers and partners. Listen to exciting panel discussions on current design topics.
Enter to win an hourly drawing for a FlipVideo camcorder!
Ecosystem Booth Schedule
Demo Suites
Booth 3751 (North Hall)
Choose from a variety of live product and flow demonstrations. In the Cadence demo suites, you’ll see the latest advances in system-level design, transaction-level modeling, enterprise verification, power-efficient design, advanced node adoption, model-based design for manufacturing, and mixed-signal solutions.
Sign up for demos now! »
ChipEstimate.com
Booth 1100 (South Hall)
The ChipEstimate.com chip planning portal is an ecosystem comprising more than 200 of the world's largest IP suppliers and foundries. These companies all share a common vision of helping the global electronics design community achieve greater profitability and success. To date, more than 80,000 chip estimations worldwide have been performed by designers, architects, and managers who rely on the ChipEstimate.com chip planning portal. All within this one site, which provides free registration to the design community, users can explore an extensive catalog of semiconductor design and verification IP and download the InCyte Chip Estimator Starter Edition tool to predict die size, power, leakage, performance, and cost of their next chip design.
At the ChipEstimate.com exhibit, you’ll learn about the latest in semiconductor IP from dozens of IP suppliers on the IP Talks! stage. Join us for hands-on demonstrations of IP exploration and chip estimation and discover how to estimate your next chip's size, power, and cost—in mere seconds. To see a schedule of participating IP partners, visit www.ChipEstimate.com. (Chip Estimate is a subsidiary of Cadence Design Systems, Inc.)
Learn more in the IPTalks! video »
Cadence at IBM Booth
Booth 4311 (North Hall)
The IBM Electronics Verification Management Solution (EVMS), built on product offerings from IBM and Cadence, is a fully integrated solution to address the issues facing SoC verification. Learn how you can use this to manage an enterprise verification environment to achieve fewer respins while managing schedule predictability.
Cadence at OVM World Booth
Booth 3450 (North Hall)
The Open Verification Methodology (OVM) is the industry’s only truly open and interoperable solution, guaranteed to run on multiple leading simulators and support multiple languages.
Jointly developed by Cadence and Mentor Graphics, the OVM is now supported by an extensive ecosystem of more than 50 partners providing products, services, and training.
The OVM also facilitates easier verification reuse and the development and usage of plug-and-play verification IP written in the SystemVerilog, SystemC, and e languages.
The OVM World exhibit is a one-stop site for OVM news and information as well as downloads of the OVM open source library, documentation, and extensive community contributions. You’ll hear from partners and users from this community, sharing their OVM successes.
Cadence at Si2 Booth
Booth 1400 (South Hall)
Cadence Design Systems will demonstrate solutions using several widely-deployed Si2 standards – OpenAccess, Common Power Format, and ECSM. Hear from experts how you can use these industry-leading solutions from Cadence to address your most challenging mixed-signal, low-power, or advanced-node design problems.
Cadence at Tela Innovations
Booth 710 (South Hall)
Cadence and Tela Innovations collaborate to offer you the latest in lithography-optimized design solutions. See a demo of how Cadence NanoRoute® advanced node routing technology (including 1D routing and lithography hotspot prevention) and Tela Innovation's on-grid, straight-line, 1D layout structures result in significant improvements in manufacturability and performance.
Cadence at TSMC Open Innovation Forum Booth
Booth 822 (South Hall)
Come and see how Cadence and TSMC collaborate so you can innovate! Cadence will demonstrate the results of its long-standing collaboration with TSMC to enable predictable SoC design to meet today’s time-to-volume requirements. The TSMC Reference Flow 10.0 offers unique system-in-package (SiP), substrate noise analysis (SNA), and integrated model-based DFM capabilities to implement advanced nanometer SoCs successfully. Cadence will also showcase a joint RF Reference Kit recently released by TSMC and Cadence, enabling a predictable AMS/RF design flow.
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