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 Cadence Member: About TeamESL 

TeamESL   | 315 points
San Jose, CA
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Member since: February, 2009
Bio The "Team ESL" blogging core team is:

Neeti Bhatnagar
Sr. Engineering Manager,
i.e SystemC simulation, analysis, debug engineering projects, as well as herding cats.

Stuart Swan
Sr Architect
i.e. Lead Cadence contributor to creation of the OSCI SystemC simulator and active participant in OSCI committee work

Dr. Sergio Ramirez is a Senior Staff Product Engineer on the C-to-Silicon Compiler team. A professor, technologist, and patent holder, Dr. Ramirez not only educates, he entertains!

Guy Mosenson
Sr Architect
i.e. Creating methodology for TLM Design and Verification,, including IP creation and reuse of TLM Design and Verification IP

Mark Warren
Engineering Director,
i.e. Guiding C-to-Silicon into the marketplace, transforming customer methodology from RTL to a TLM-driven design approach

Leonard Drucker
Core Comp Architect
i.e. Virtual Prototyping and SystemC design and verification expert

Robert Juliano
Core Comp Sr Technology Leader
i.e. Crafting the synthesizable subset definition for SystemC support in C-to-Silicon, including the verification performance implications therein

Jean-Michel Fernandez
Core Comp Architect
i.e. Developing innovative SystemC-based solutions for architectural analysis and transaction level functional verification

Additionally: this team will be frequently be joined by "guest bloggers" from C-to-Silicon, Incisive, and Chip Planning System R&D (to give you glimpses of what's going on under the hood), and our colleagues from the Cadence Field organization (to share with you what trends they are seeing in their territories).
Academic Background No profile info has been provided Organization Affiliations OSCI, SPIRIT Community Interests System Design and Verification
Personal Interests No profile info has been provided Publications Website:  www.cadence.com/products/sd/Pages/default.aspx
Blog:  www.cadence.com/community/blogs/sd/
My Friends
Ran Avinun
Steve Brown

Creating SystemC TLM-2.0 Peripheral Models
by TeamESL

Understanding Latency versus Throughput
by TeamESL

More Details on Post Silicon Embedded Software Verification With ISX
by TeamESL