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Xilinx
DAC2012: Xilinx Zynq-7000 - From RTL to Success with Emulation
It is nice to see when visions get closer to reality. When Cadence announced its vision for the System Development Suite back in 2011, offering a continuum of engines from virtual prototyping through RTL simulation, acceleration and emulation all the way to FPGA based prototyping seemed aggressive. Or...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Mon, Jul 2 2012
DAC 2012: The Top Seven Reasons for using FPGA Based Prototyping
John Blyler, Editorial Director at Extension Media , presented in our EDA360 Theatre at DAC 2012 about "ASIC/ASSP Prototyping with FGPAs" and provided an update on his annual survey on this topic. The current 2012 survey is actually currently ongoing and you can still participate here . FPGA...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Thu, Jun 28 2012
DAC 2012: Enabling the Programming of an Extensible Processing Platform
We at Cadence have been writing about the virtual prototype associated with the Xilinx Zynq-7000 Extensible Processing Platform (EPP) quite a bit. At the recent Design Automation Conference (DAC) it was our pleasure to welcome Dave Beal from Xilinx in the EDA360 Theatre to talk about Zynq, its programming...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Tue, Jun 26 2012
DAC 2012: Connecting Emulation to the Real World of Wireless Interfaces
This is certainly the most connected DAC I have been to so far. Tweets and connections everywhere, blogging is happening left and right. A lot of the attendees hold their wireless devices in their hands. It is rewarding that we are part of enabling all that. Living proof of that came today from our System...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Tue, Jun 5 2012
DAC 2012 Gary Smith EDA Kickoff: EDA and ESL Growth and Four Different Software Virtual Prototypes
DAC 2012 kicked off yesterday with the annual DAC Reception followed by Gary Smith's keynote detailing challenges in EDA. For system-level design there was some really good news, but also some interesting detailed refinement on how much effort virtual prototyping for enablement of software development...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Mon, Jun 4 2012
DAC 2012: Handling a Double Paradigm Shift for Embedded Software Development
Change is hard. And we in product marketing for development tools are trying to cause change and find out if and how users are adopting new methodologies and tools. A little over a year ago, in the spirit of fellow Blogger Steve Leibson's law, that "it takes 10 years for any disruptive technology...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Mon, Jun 4 2012
Being The Energizer Bunny at DAC … Championing System-Level Design and Verification ;)
As the EDA industry and its customers are preparing for the yearly show down at the Design Automation Conference (DAC), it is good to review what I said in the past. Well, two years ago I wrote a blog called "Maybe This Time" ( inspired by the Sally Bowles song in Cabaret , I am a Musical Geek...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Fri, Jun 1 2012
TLM Design and Verification: What to See at DAC This Year
If you are attending the Design Automation Conference ( DAC 2012 ) June 4-7 in San Francisco and you are interested in SystemC/TLM driven design and verification, including high-level synthesis, there are a lot of interesting sessions. First, there is a parallel conference going on Saturday and Sunday...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Thu, May 31 2012
How Will High-Level Synthesis Affect the Make vs. Buy vs. Re-use Decision?
During the planning phase for SoC designs, teams have to choose whether to "make or buy" the pieces of IP that will compose the SoC. The drivers of this decision are well-chronicled in a recent article by Ann Steffora Mutchler, appropriately titled "Make vs. Buy". I won't re-hash...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Tue, Nov 22 2011
Welcome to the Zynq-7000 Virtual Platform
As you might guess we are pretty excited about the Virtual Platform development for the Zynq-7000 EPP . The FPGA world has changed a lot from 1995 when I was an FAE at Cypress Semiconductor selling and supporting programmable logic devices. This was during the transition from schematic capture to HDLs...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Fri, Oct 28 2011
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