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rtl compiler

Cadence, ARM, Samsung 14nm Test Chip – Collaboration Eases FinFET Digital Implementation

A recent test chip tapeout using the Samsung 14nm FinFET process revealed significant progress in digital implementation at this new process node. Thanks to deep collaboration and extensive R&D investments in libraries, process, and tools, the digital implementation of the test chip was successfully...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 7 2013
C-to-Silicon 12.2 Available for Your Holiday Shopping List

The winter holiday season is that special time of year when we get bombarded with catalogs, emails, television commercials, banner ads, store displays, and any other method to get our attention on something that somebody is trying to sell. Having been trained as an engineer, I'm able to filter a...

Posted to System Design and Verification (Weblog) by Jack Erickson on Thu, Dec 13 2012
Register for Cadence's Front End Design User Summit -- December 6, 2012 in San Jose

Cadence is hosting a Front End Design Summit on Thursday, December 6, 2012 9:30am – 5:00pm at Cadence San Jose headquarters, 2655 Seely Avenue, Building 10. Logic designers will hear from customers including Cisco, Chelsio, PMC, Spansion, and Via Technologies about strategies they employed to overcome...

Posted to Logic Design (Weblog) by Kenneth Chang on Tue, Nov 27 2012
ARM Blog Tells Story of a 20nm Cortex-M0 Test Chip

All 20nm test chips are learning experiences, and a recent tapeout of a 20nm Cortex-M0 test chip by ARM engineers was no exception. Completed in June 2012, the test chip design used a Cadence digital implementation flow. The story of the test chip is told in a new guest partner blog (I'm the "guest"...

Posted to Industry Insights (Weblog) by rgoering on Tue, Nov 27 2012
CDNLive paper: High-level Synthesis on Video Processing ASIC

The proceedings from the recent CDNLive! event in Israel recently became available, and you can access them with your Cadence.com account login. The paper entitled "High-level Synthesis on Video Processing ASIC" delivered by Yaniv Fais and Michael Zarubinsky of Freescale gives a great look...

Posted to System Design and Verification (Weblog) by Jack Erickson on Wed, Nov 14 2012
Re: gray code

Hi gh-, RTL Compiler has no support to control FSM coding style. I vaguely remember even Synplify had a pragma for this (binary, one-hot, gray or Johnson coding). I have done an experiment: Synthesized 9-bit binary counter, and then synthesized 9-bit Gray counter (using CW_cntr_gray) using following...

Posted to Digital Implementation (Forum) by Sporadic Crash on Mon, Oct 29 2012
Re: gray code

I am interested in Gray coding with RTL Compiler. In the tool following synthetic operators are used: BIN2GRAY_STD_LOGIC_OP, GRAY2BIN_STD_LOGIC_OP, INC_GRAY_STD_LOGIC_OP Additionally, following ChipWare components are related to Gray codes. CW_inc_gray, CW_gray2bin, CW_cntr_gray, CW_bin2gray There is...

Posted to Digital Implementation (Forum) by Sporadic Crash on Wed, Oct 24 2012
Margins are Costly - Don't Let Them Grow Out of Control!

Last week, Professor Jan Rabaey of the University of California at Berkeley gave a great keynote at Cadence's Low Power Technology Summit that called for changes to the conventional solutions for power reduction. One of the points he made was that today's designs are over-designed and over-constrained...

Posted to System Design and Verification (Weblog) by Jack Erickson on Wed, Oct 24 2012
Q&A: Phil Bishop, New Cadence VP, Drives Adoption of System-Level Design

Phil Bishop has come into his new role - Vice President and General Manager of System Level Design at Cadence - at an exciting time. After years of slow growth, technologies such as high-level synthesis and virtual prototyping are seeing adoption and showing results in more and more production environments...

Posted to Industry Insights (Weblog) by rgoering on Mon, Oct 8 2012
Digital Logic in Analog Block – How Will You Test It?

Analog IP blocks these days have increasing amounts of digital control logic. With very small amounts of digital logic, it's possible to just draw gates on the schematic and run targeted tests that will hopefully catch any errors. But when you have several thousand digital gates, a new approach is...

Posted to Industry Insights (Weblog) by rgoering on Mon, Sep 10 2012

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rtl compiler

Cadence, ARM, Samsung 14nm Test Chip – Collaboration Eases FinFET Digital Implementation

C-to-Silicon 12.2 Available for Your Holiday Shopping List

Register for Cadence's Front End Design User Summit -- December 6, 2012 in San Jose

ARM Blog Tells Story of a 20nm Cortex-M0 Test Chip

CDNLive paper: High-level Synthesis on Video Processing ASIC

Re: gray code

Re: gray code

Margins are Costly - Don't Let Them Grow Out of Control!

Q&A: Phil Bishop, New Cadence VP, Drives Adoption of System-Level Design

Digital Logic in Analog Block – How Will You Test It?