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mixed-signal,advanced node

  • What’s Hot for Mixed-Signal At DAC?

    Analog/mixed-signal design is a hot topic at the Design Automation Conference! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), you can keep up with the latest developments in mixed-signal design methodology, including design, implementation and verification. You will find it is...
    Posted to Mixed-Signal Design (Weblog) by QiWang on Thu, May 31 2012
  • Rapid Analog Prototyping - Handcrafted Layout Gets a Needed Productivity Boost

    As more and more custom/analog designs migrate to advanced process nodes (<65nm), design teams are being confronted with an ever-increasing need to better manage the impact of parasitics throughout the entire custom/analog design flow. In addition, more and more layout design teams are finding themselves...
    Posted to Custom IC Design (Weblog) by mrkelly on Thu, Mar 17 2011
  • Q&A Interview: Charlie Giorgetti Outlines Cadence Product Solutions

    Charlie Giorgetti is corporate vice president of solutions and product marketing at Cadence. In this interview, he discusses Cadence’s product strategy, and outlines five “solutions” that are the current focus of Cadence’s marketing efforts. These solutions will be highlighted...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Jul 23 2009
  • Simulation of Voltage Scaling for Dynamic Power Reduction

    Some background info: In a previous blog , I introduced: DVFS (Dynamic Voltage and Frequency Scaling), a technique used for Dynamic Power Reduction. RVM (Real Valued Modeling) for efficient simulation of mixed signal SoC with very high speed and efficiency using Cadence DMS (Digital Mixed Signal) offerings...
    Posted to Functional Verification (Weblog) by Neyaz on Wed, Jul 22 2009
  • DesignCon 2010 Call for Papers

    Hello, As a member of the technical committee and as the chair member for the Analog and Mixed-Signal Design and Verification track, I would like to invite you to submit an abstract to this conference. We solicit papers for two types of sessions: technical papers and tutorials. Technical papers, which...
    Posted to Custom IC Design (Weblog) by helenet on Mon, Jul 20 2009
  • Using wreals to Simulate Frequency Scaling for Dynamic Power Reduction

    Some background info: Taking a quick look at Power dissipation in CMOS: Leakage power is well managed by powering down parts of the design when not in use. This is a well understood problem and can be simulated well in IUS (Incisive Unified Simulator) using CPF (Common Power Format) commands to capture...
    Posted to Functional Verification (Weblog) by Neyaz on Wed, Jul 15 2009
  • Guest Blog: The RF Challenge In Portable Designs

    The need for RF integration in consumer electronics presents some tough challenges, says veteran electronics industry editor John Donovan. He notes several emerging approaches that might help ease the challenge. In simpler times most designs were digital. Add a few converters to handle I/O and you could...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jul 13 2009
  • Q&A Interview: Chi-Ping Hsu Describes 5 Cadence Initiatives

    Chi-Ping Hsu is senior vice president of research and development for the Cadence Implementation Products Group. He is responsible for analog design and verification, digital implementation and signoff, mixed-signal design and implementation, physical verification, DFM, and PCB and package design. In...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Jun 25 2009
  • Cadence: Committed to DFM

    On June 10, Cadence issued a press release that mentioned “…decreasing the level of investment in the manufacturing side of DFM” as part of restructuring activities. Since that announcement, some in the press and analyst community have published their interpretations of the actions...
    Posted to Digital Implementation (Weblog) by mchacko on Fri, Jun 19 2009
  • Analog Is Back – But Not Like You Think

    After taking a back seat to digital design for many years, analog is re-emerging as a key differentiator and competitive edge for IC vendors. But analog design today is very different from that of 20 years ago, and realizing that is critical for success. In a recent EE Times column , Planet Analog editor...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Jun 18 2009
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