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cpf,power

  • New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF

    On May 7, 2013 Cadence announced a 30% productivity gain in the June 2013 Incisive Enterprise Simulator 13.1 release . Advanced debug visualization, faster turn-around time, and the extension of eight years of low-power verification innovation to IEEE 1801/UPF are the key capabilities in the release...
    Posted to Low Power (Weblog) by Adam Sherilog on Tue, May 7 2013
  • Panel: Integrating Low-Power ARM Processors into Mixed-Signal Designs

    Mixed-signal chip designs with embedded digital signal processing are becoming more and more commonplace these days. How can you bring low-power processors, such as the ARM Cortex-M0 , into such designs quickly and efficiently? A lunch panel discussion at the recent Design Automation Conference (DAC...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Jun 20 2012
  • What’s Cool for Low-Power at DAC?

    Low-power design promises to be a key theme of the Design Automation Conference once again! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), if you need to cover design, implementation and verification of this important subject, there's a lot to choose from at Cadence's...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, May 30 2012
  • System-Level Low Power Design – What Will it Take to Move There?

    While many low-power design techniques are available to IC designers, the greatest potential for power savings is at the system level, where both software and hardware can be considered. So what's standing in the way of system-level low power design, and what needs to happen to make it practical...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Apr 18 2012
  • Webinar Report: Power-Aware Mixed-Signal Verification

    Most of the discussion about low-power design techniques has focused on digital circuits. However, nearly all systems-on-chip (SoCs) are mixed-signal, and the way in which analog and digital circuitry interact has a huge impact on overall power consumption. Thus, low power (or "power aware"...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 25 2012
  • What’s Next in Low Power?

    Low power has become a major consideration in chip design in almost all applications. One major achievement of the industry over the past a few years is the alignment on the low power design methodology, which was considered as the biggest hurdle to automate advanced low power design techniques. No matter...
    Posted to Low Power (Weblog) by QiWang on Tue, Jan 24 2012
  • Si2 Interoperability Guide V2.0 Available for Download

    Recently, the Silicon Integration Initiative (Si2) announced the availability of the Interoperability Guide for Power Format Standards V2.0 . This is an important milestone of power format interoperability between IEEE 1801-2009 and the Common Power Format (CPF). This update was triggered by the Si2's...
    Posted to Low Power (Weblog) by QiWang on Mon, Oct 31 2011
  • Another Expert’s View on Power Intent and Hierarchy

    Normal 0 false false false EN-US X-NONE X-NONE /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, Sep 21 2011
  • User View: Low Power Challenges at 40nm and Below

    Low power design is hard enough at 65nm and above, and it poses additional challenges at 40nm and below, according to Alex Kuo, department manager at SoC design firm Global Unichip Corp. As noted in another Cadence Community blog post by Qi Wang, Kuo offered a presentation on low-power design at the...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Jun 21 2011
  • Power Modeling Standards Effort Aims to Ease IP Integration

    A new standards effort that could ease low-power silicon IP integration is quietly underway at the Silicon Integration Initiative (Si2) Low Power Coalition ( LPC ). Although the LPC is probably best known as the home of the Common Power Format (CPF) originated by Cadence, it actually has a much broader...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 26 2011
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