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  • Incisive Formal Verifier

    Hi all, I have been working on ifv tool for connectivity verification. I have passed blackbox list file to ifv which includes one of the modules that is responsible for system ready signal. I need to do this because I am checking connectivity for some of the signals which are part of that module. If...
  • Free DAC Breakfast and Luncheons – Mixed Signal, Software-Driven Verification, Cross-Fabric, and High-Performance Digital

    Whoever said "there is no such thing as a free lunch" has not been to the Design Automation Conference ( DAC 2014 ). This year at DAC, Cadence is sponsoring one breakfast and three luncheons that will include presentations or panels on four emerging challenges - mixed-signal power management...
    Posted to Industry Insights (Weblog) by rgoering on Tue, May 20 2014
  • DDR4 in 16nm FinFET: Future-Proof Your SoC Design

    Cadence this week (May 19, 2014) is announcing the first DDR4 PHY IP built on TSMC's 16nm FinFET process. The 3200Mbps DRAMs that can take best advantage of this capability aren't shipping in volume yet - but you can "future-proof" your 16nm SoC design by using a DDR4 controller and...
    Posted to Industry Insights (Weblog) by rgoering on Mon, May 19 2014
  • Impedance measurement

    Sir/Madam, I have been designing a Differential drive rectiifer for UHF passive RFID in 130nm CMOS process. As the design of rectifier completes I got stuck with the impedance measurement, i.e. for finding input impedance of rectifier using Cadence Virtuoso. As it is a non-linear circuit which simulation...
    Posted to RF Design (Forum) by Jithin on Mon, May 12 2014
  • Help with complete understanding of "vsin" source in Cadence

    Hi. I kind of thoroughly Googled before posting this question for seeking help from you guys! The "vsin" source (in analogLib) of Cadence has many parameters: i) AC magnitude, AC phase, DC voltage ii) Offset voltage, Amplitude, Frequency,... Question 1: Internet resources are indicating that...
    Posted to Custom IC Design (Forum) by jdp721 on Sun, May 11 2014
  • IoT's Promise Shadowed by Privacy Questions

    The Internet of Things (IoT) will help society do more with less, drive efficiencies, and light a fire under economic growth, but concerns around change-averse industries and user privacy may delay that promise. That was the take-away from a World Affairs Council panel held at Cadence May 7. The sold...
    Posted to The Fuller View (Weblog) by Brian Fuller on Fri, May 9 2014
  • Can a beginner ask here for some help?

    Hi, I am a student at local faculty of Electrical Engineeing, and I just recently started using Cadence Virtuoso. The thing is, I am also employed, and I'm attending this course in RF electronics at the department which I don't belong to. We had a couple of lab exercises till now, using Virtuoso...
    Posted to RF Design (Forum) by Lajka on Thu, May 8 2014
  • Cadence DAC 2014 and Denali Party Update

    The 51 st Design Automation Conference (DAC) will take place June 1-5 in San Francisco, and Cadence is preparing a number of activities. This year Cadence is participating in technology sessions, customer/partner presentations, papers and panels, and three lunches and one breakfast. And of course, the...
    Posted to Industry Insights (Weblog) by rgoering on Sun, May 4 2014
  • Cloud Computing Design Challenges: An Engineering Journey

    Earlier this year, we explored cloud computing and application-specific systems design, as Cadence Fellow Chris Rowen urged us to " follow the data " to understand evolving electronics-design dynamics. Now comes Ron Wilson , Altera's editor-in-chief, who writes about heterogenous computing...
    Posted to The Fuller View (Weblog) by Brian Fuller on Thu, May 1 2014
  • cadence pz analysis

    for a two stage opa as Allen described,with a compensation cap,with the cadence pz analysis,found that there are 5 poles,5 zeros ,is that right? somebody said that should cancel some pole-zero pair,how should I do that? Is the pz analysis correct? How others usually do? that I have another question,I...
    Posted to RF Design (Forum) by jasonxian on Thu, Apr 24 2014
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