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Upcoming Webinar: SoC Verification Challenges in the IoT Age
By Brian Fuller on July 11, 2014
ARM and Cadence host a webinar July 22 to explore how electronics design teams can tackle Internet of Things (IoT) and (SoC) design and verification challenges.... Read more »
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What's Your Summer Engineering Project?
By Brian Fuller on July 09, 2014
Summer engineering projects can be fun and teach you a lot about yourself you never knew.... Read more »
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EDA Plus Academia: A Perfect Game, Set and Match
By Steven Lewis on July 08, 2014
Excuse the tennis analogy, but just coming out of Wimbledon! However, EDA and academia have had a long-standing tennis match, if you will, in which there is a "give and take" between the EDA world and the many universities around the world.... Read more »
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Whiteboard Wednesdays - Verifying Solid State Drives Incorporating NVM Express
By Corrie Callenbach on July 08, 2014
In this week's Whiteboard Wednesdays, Mukul Dawar explains the NVM Express protocol and considerations to keep in mind when using verification IP to perform functional verification.... Read more »
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IP Talks! Keynote at DAC 2014—Rethinking Image Processing in SoC Design
By Richard Goering on July 07, 2014
Many systems on chip (SoCs) have a "camera block" or image signal processor (ISP) that takes raw data from an image sensor and manipulates that data. But ISPs are moving away from their traditional role and turning into "vision subsystems... Read more »
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Virtuosity: 21 Things I Learned in May and June 2014 by Browsing Cadence Online Support
By Stacy Whiteman on July 03, 2014
Application Notes 1. Setting PVS to QRC av_extracted Flow with tsmc28 (& tsmc40 ) LVS Shows you how to put in place the PVS(LVS)-QRC(av_extracted) view using TSMC files. Videos 2. Mismatch Contribution in Virtuoso Analog Design Environment GXL Mismatch... Read more »
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