Home > Community > Blogs > Industry Insights
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Industry Insights Blog

Designer View – Getting the Best Use From Static Low-Power Verification

Do you want assurance that your system-on-chip (SoC) netlists are "power clean?" In a recorded presentation on the Cadence web site, Harshat Pant, principal engineer at Broadcom, shows how static low-power verification can provide that assurance...  Read More »
Comments (0)
Filed under: , , , , ,
Sean Dart Q&A: Former Forte CEO Discusses Past, Present, and Future of High-Level Synthesis

Earlier this year Cadence acquired Forte Design Systems , a pioneer of high-level synthesis (HLS) and provider of the Cynthesizer SystemC-based synthesis tool. Sean Dart, Forte CEO since 2006, is now senior group director for R&D at the Cadence System...  Read More »
Comments (1)
Filed under: , , , , , ,
Protium FPGA-Based Prototyping Platform – Speeding Bring-Up Times

FPGA-based prototypes provide excellent platforms for pre-silicon software development - but prototype bring-up times are so long and painful that much of the value is lost. Promising to shorten bring-up times by up to 70% versus competing commercial...  Read More »
Comments (0)
Filed under: , , , , , , ,
Quantus QRC Extraction Solution – Massive Parallelism Extracts Accurate Parasitics Quickly

Over the past 14 months Cadence has brought massive parallelism to static timing analysis ( Tempus Timing Signoff Solution ) and power analysis ( Voltus IC Power Integrity Solution ). Today (July 14, 2014) Cadence is announcing the Cadence Quantus QRC...  Read More »
Comments (0)
Filed under: , , , , , , , ,
IP Talks! Keynote at DAC 2014—Rethinking Image Processing in SoC Design

Many systems on chip (SoCs) have a "camera block" or image signal processor (ISP) that takes raw data from an image sensor and manipulates that data. But ISPs are moving away from their traditional role and turning into "vision subsystems...  Read More »
Comments (0)
Filed under: , , , , , ,
DAC 2014 Panel: FinFET IC Design Poses No Roadblocks, but Lots of Details

FinFET transistors promise enormous power and performance advantages at process nodes below 20nm, but how will they impact IC design? If you're a digital designer, not much changes - but if you're a custom/analog designer, there's a lot to...  Read More »
Comments (0)
Filed under: , , , , , , ,
DAC 2014: 30+ Customer, Partner Presentations Now Available on Cadence.com

One of the busiest spots on the Design Automation Conference (DAC 2014) show floor was the Cadence Theater, which featured continuous customer and partner presentations over a three-day period June 2-4. These informal, half-hour presentations allowed...  Read More »
Comments (0)
Filed under: , , , ,
DAC 2014: High-Level Synthesis (HLS) Users Share Advantages, Challenges

High-level synthesis (HLS) is an emerging IC design technology that promises huge productivity gains, but you need to understand its advantages and limitations before diving in. The best way to get that understanding is to listen to the experiences of...  Read More »
Comments (0)
Filed under: , , , , ,
China Fabless Semiconductor Panel: Don’t Pack Your Bags Just Yet

Has the center of gravity for system on chip (SoC) innovation shifted to China? If you're planning to start a fabless semiconductor company, should you pack your bags, leave Silicon Valley, and head for Shenzhen or Shanghai? Not so fast, according...  Read More »
Comments (0)
Filed under: , , , , ,
Accellera DAC 2014 Breakfast—What Engineers Really Think About UVM

The Universal Verification Methodology ( UVM ) has compelling advantages for IC verification but can be challenging to adopt, according to panelists from four user companies at an Accellera breakfast at the recent Design Automation Conference (DAC 2014...  Read More »
Comments (0)
Filed under: , , , , ,
View older posts »
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.