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C-to-Silicon Japan User Group and Ikegami Production Experience

Comments(0)Filed under: C-to-Silicon Compiler, High-Level Synthesis, ESL, SystemC, FPGA, synthesis, hls, japan, customers, Ikegami, Virtex-6, Maesato, Japan user group

We have been seeing some rapid growth in adoption of C-to-Silicon Compiler high-level synthesis. Given that it is a new way of doing design, we have been holding user local groups to get customers together with Cadence people to share experiences, information, and ideas so that we can all benefit.

We have held these user groups so far this year in Israel, Japan, and internally to a large customer. To give an idea as to what is typically covered, we can look to Japan which hosted the most recent one.

The morning session was open only to active customers of C-to-Silicon. There were about 25 of them, and they were treated to a tips and tricks session led by one of Cadence's leading  applications engineers. This was followed by a roadmap session from a Cadence solutions architect, outlining our plans for further development of generic point-to-point communications interfaces.

The afternoon session was open to both existing and prospective customers, and over 30 new attendees joined, bringing the total to over 55. The highlight of this session was a presentation by Maesato-san of Ikegami. Those outside of Japan may not be familiar with Ikegami, but they make television cameras, studio monitors, and other broadcast equipment. The chip covered in this presentation was for a studio television camera and targeted to a Xilinx Virtex-6 FPGA. It was designed by 7 engineers, 6 of whom were novices to high-level synthesis.

They chose high-level synthesis and C-to-Silicon not only to improve design and verification productivity, but also because they wanted the design to be more easily re-used. They ended up designing 97% of the 8.7M gates with SystemC and C-to-Silicon; the rest were IP blocks. They were able to achieve 150 MHz on the Xilinx device, and when experimenting with retargeting for a 90nm ASIC, they managed raise the frequency to 300Mhz and reduce the power to 1/7th  of the original. From a verification standpoint, Maesato-san said that they were able to detect 95% of the defects at the algorithm verification stage before RTL simulation.

Overall, Ikegami achieved their targets for frequency, throughput, and area. And most importantly they were able to very easily re-target the design from the intended FPGA to their experiments with the ASIC. Maesato-san requested some improvements to C-to-Silicon, but gave it a passing grade overall.

With high-level synthesis still such a new technology and methodology to most designers, sessions like these where new and existing customers can share experiences are extremely valuable. We will continue to hold these regionally where and when it makes sense, and if you would like to participate please contact your local Cadence representatives or you can contact me directly.

-Jack Erickson

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