This is the fourth in a series of discussions we would like to open up regarding “favorite features” in an IC Packaging implementation design tool.
While wirebond packages are nothing new, the challenges associated with package designs using wirebonds have continued to grow. Stacking die in low profile packages that can go into a number of consumer devices has become more and more common. It seems every wirebond design contains more wires with less space – not only in the X/Y direction, but also less space in the Z direction Without a DRC engine to maintain spacing as you move wires around in the bonding pattern, it would be a nightmare to complete today’s complex stacked die designs. In addition, with stacked die, or multiple tier single die designs, the ability to make sure wires maintain spacing in a Z direction is also a key requirement.
Fortunately, Cadence IC Packaging products have evolved along with the challenges and are now actively used by the vast majority of package designers doing wirebond designs today. In addition to managing the wirebond pattern and 3D DRCs, designers can now utilize efficient routing technology to speed the time it takes to complete the full package design. To get just a glimpse of many of the wirebond features available in Allegro Package Designer and Cadence SiP, take a few minutes to watch this video:
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Let us know what wirebond challenges you’ve faced while designing wirebond packages.