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What's Good About Differential Pairs in Allegro Constraint Manager? See For Yourself in SPB16.3!

Comments(0)Filed under: PCB Layout and routing, PCB design, SPB, Differential Pair Support, Allegro PCB Editor, Allegro, differential Pair Swapping, PCB Editor, PCB, SPB 16.3, reflection, DRC, Allegro 16.3, SPB16.3, Library, Constraint-driven PCB Design flow, DDR2, differential pairs, diff pairs

There are a couple new Differential Pair (Diff Pair) capabilities available with the SPB16.3 Allegro PCB Editor Constraint Manager - Differential Pair Renaming and Dynamic Phase Control for Differential Pairs.

Differential Pair Renaming

Prior to the SPB16.3 release, library and model-defined differential pairs are automatically named based upon the member nets of the differential pair. However, you might want to rename differential pairs based on specific naming conventions. Until now, you could rename only user-defined differential pairs in Constraint Manager. In the SPB16.3 release, Constraint Manager extends the support for renaming all types of differential pairs.

Constraint Manager (CM) now supports renaming of all DiffPair types (user, library, and model) using commands. When renaming a library or model defined DiffPair, the rename dialog contains a new Use default button which allows you to revert to the auto-generated name. This button will not be visible for user-defined DiffPairs.

In CM, model defined differential pairs are denoted as Type Dpr(M):

These differential pairs can now be renamed using Objects > Rename or RMB > Rename.

A dialog box is presented, allowing you to rename the differential pair.

The Use Default button resets the differential pair name back to its default value.

Dynamic Phase Control for Differential Pairs

Differential Pair (Diff Pair) technology has evolved where more stringent checking is required in the area of phase control. This is evident on higher data rates associated with parallel buses such as QPI, SMI, PCI Gen 2, DDR, QDR and Infiniband. In the simplest of terms, Diff Pair technology is sending opposite and equal signals down a pair of traces. Keeping these opposite signals in phase is essential in assuring that they function as intended. As the current “Static Phase” is limited to a one time check across the entire Driver-Receiver path, a new “Dynamic Phase” check is introduced that performs phase checks at bend point intervals across the Diff Pair.

The Dynamic Phase check is designed to meet the guidelines that suggest that the path lengths of the true and complement signals within the differential pair must differ by no more than “x mils” along the entire path of the net.  If at any point on the net, the skew between true and complement exceeds “x mils”, this mismatch needs to be compensated within “y mils”.  Representative values for x and y might be x = 20 and y = 600. 

The constraints associated with Differential Pairs now support Static and Dynamic Phase. The margins of each constraint can be set independently using length or time. The Max Length (running skew) constraint for Dynamic Phase is limited to length only.


  • Static Phase Tolerance – a one time check from Driver to Receiver comparing lengths or delay of each member. If a Driver cannot be determined, the check is performed across the longest path of the pair. There is no change in this behavior in the SPB16.3 release.
  • Dynamic Phase – Etch length of each member is compared at each bend point interval across the Driver-Receiver path of the Diff Pair. Etch length is always measured back to the Driver pins.
  • Dynamic Phase Max Length – When specified, the Diff Pair is permitted to exceed the phase tolerance constraint for a contiguous etch length of less than or equal to the value of Max Length specified. If no compensation is made within this specified distance, a DRC will be reported at the point where the Diff Pair first goes out of phase.

As an example, suppose your Dynamic Phase constraints are set as follows:

When the DRC is updated, it shows the following:

The beginning of the yellow pseudo line (closest to driver) is where the Diff Pair initially goes out of Phase (beyond the 20 mil tolerance). The DRC marker D-Y is placed at the initial ‘out of phase spec' location as measured from the Driver Pins.


  • There can only be 1 DRC marker on a pair, even though there may be multiple violation zones.
  • It is assumed that the designer will correct the phase issues working from the Drivers to the Receivers.

Please share your experiences with this new SPB16.3 capability!

Jerry "GenPart" Grzenia


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