At CDNLive-Silicon Valley this year, we had an excellent mixed-signal track for two days. Cadence customers including IBM, Texas Instruments, Maxim and Freescale shared their mixed-signal methodologies and tricks with the Cadence design community. The key challenges that our mixed-signal customers face are in SoC level verification and seamless analog/digital implementation. Cadence has been addressing these challenges for the last few years with its focus on mixed-signal solutions. Cadence's Mixed-Signal Methodology book has garnered tremendous interest from the worldwide mixed-signal design community.
In order to cater to the design community in North America, we will present a series of Mixed-Signal Tech on Tours to showcase and address mixed-signal challenges and show how Cadence's mixed-signal solutions can help deisgners achieve design closure.
In the first series, we are coming to the east coast. Below are the dates and cities for MS ToTs in this series:
Ottawa, Ontario -- April 2, 2013
Baltimore, MD -- April 4, 2013
Chelmsford, MA -- April 9, 2013
You can register for any of these events here.
Key topics that willl be covered include:
To deliver these sessions, we are bringing in experts for each topic to provide excellent technical depth.
In addition to Cadence mixed-signal technologies, we are very pleased to have IBM partner with Cadence to talk about IBM's foundry and services enablement at these events.
Below is the detailed agenda for the first three Mixed-Signal Technology on Tour events at Ottawa, Baltimore and Chelmsford. I hope to meet you at these events.
Registration and Breakfast
Welcome and Opening Remarks
- Mixed-Signal (MS) Solution Overview
- MS Trends and Challenges
- MS Verification Overview
- MS Implementation Overview
- Verifying Low Power in MS design
- Static Timing Characterization for MS Ecosystem
- Mixed-Signal Simulation
- Performance and Scalability
- Use Models and Language Support
- Analog Behavioral Modeling
- Why Do I Need Modeling?
- Real Number Modeling
- Model Generation and Validation with Demo
- Simulating Embedded ARM Cortex-M0 MS Designs
- Trends in Analog Intensive MCU
- ARM Cortex-M Introduction
- HW/SW Verification Flow with Demo
- Advanced MS Verification
- Assertions, UVM-MS and Metric-driven Methodology
- Quick Turn-around Time with Cadence Analog/Mixed Signal (AMS) IP
- AMS Interface IP
- ADC's, 10G-KR PHYs
- Cadence AMS IP Portfolio
- Analog on Top (AoT) MS Implementation Flow
- AoT Flow Overview
- Virtuoso Floorplanning and Analog Layout
- Digital Block Synthesis and Implementation in RC/EDI
- Chip Integration and Signoff
IBM Foundry Services and Design Enablement
- Digital on Top (DoT) MS Implementation Flow
- DoT Flow Overview
- Constraint (Routing) Exchange and Validation with Demo