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Tidbits From TSMC Q209 Earnings Call - 40nm Yield

Comments(1)Filed under: Litho-aware design, CMP-aware design , Physical verification, Chip Optimization, Design for yield, Silicon Signoff and Verification

Earning calls sure are interesting! Below is an excerpt from the TSMC Q209 call (transcript from seekingalpha). The discussion revolves around the 40nm yield issues and TSMC's ramp to improving the yield.

Dr. Liu really hits on a key element of DFM - which is design/layout dependency. Simply put, rule-based techniques are insufficient. To maximize yield, you need to augment with model-based techniques to be able to predict and optimize any given design. Think of model-based techniques as a virtual fab where you can analyze your design and predict the silicon behavior - without actually going to silicon.

Given this, the recent DFM checking mandates, the increased focus on variability control in Reference Flow 10... projects need to consider Manufacturability and Variability in their flow and schedules

[Excerpt from Q209 Earnings Call]

Christopher Muse - Barclays Capital

Okay, great. And then I guess last question for Mark Liu, I appreciate your comments on the 40-nanometer yield challenges. I was wondering if you could elaborate on your defect reduction methodology, where the problems lie and how you are resolving them, and what gives you the confidence you can get the yields that you are targeting in September?

Dr. Mark Liu

Okay, in this generation, what we find, what’s important is the design, layout styles because in our products, we do see the design has a -- because a different product has a different yield showing and it ranged quite widely and we find that for those products, the yield is low is mainly because of the design, layout dependence. What we call design for manufacturing. That is in plain English is when the design cannot be completely described by the design rule, we have additional algorithm software to optimize the layout so that it gets the best yield.

 

Wilbur Luo

Comments(1)

By qi-de qian on September 21, 2009
We have a linkedin group on semiconductor DFM, where you can find most of the industry leaders and university researchers.  

For those who would like to explore more please join at www.linkedin.com/groups


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